any tool for VHDL synthesizing ? 
Author Message
 any tool for VHDL synthesizing ?

Hai
    I would like to know the tools available for VHDL synthesizing.I'm
using Symphony EDA's VHDL simili (SONATA) for simulation.Does Symphony
EDA have a synthesizing tool.Kindly reply to this.

Bye
Prasanth Anbalagan



Tue, 31 May 2005 21:00:51 GMT  
 any tool for VHDL synthesizing ?

Quote:

> Hai
>     I would like to know the tools available for VHDL synthesizing.I'm
> using Symphony EDA's VHDL simili (SONATA) for simulation.Does Symphony
> EDA have a synthesizing tool.Kindly reply to this.

> Bye
> Prasanth Anbalagan

Popular synthesis tools are (random ordering):

- Synopsis Design Compiler
- Leonardo Spectrum (Exemplar)
- Synplicity Synplify

I'm afraid that in the public domain, there doesn't exist a strong candidate
to these tools. However, you could try e.g. dgc (Digital Gate Compiler), with
the project files at www.sourceforge.net or the Alliance tool from a French
university.

hope this gives you a starting point.

Uncle "The G.B. Man"



Fri, 03 Jun 2005 08:45:36 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. leonardo synthesize tool (exemplar)

2. Variables in VHDL How are they synthesized?

3. VHDL - directives for synthesize

4. synthesize hierarchical VHDL

5. How can i get the spice netlist from the synthesized netlist (vhdl netlist)

6. type declarationsin synthesized VHDL netlist...

7. Simulation with synthesized output vhdl code

8. Synthesizing RAM bank from VHDL?

9. Synthesizing RAM bank from VHDL?

10. synthesizing VHDL

11. VHDL Tool Issue or VHDL Language Question

12. Recursive VHDL models - how to prang your VHDL tools

 

 
Powered by phpBB® Forum Software