testbench. 
Author Message
 testbench.

Below is the part of my testbench. It is getting compiled but simulation
runs are not correct. Can somebody help me. Thanks,
-----------

clock: process
 constant PER: time:=40 ns;
 variable clktmp: std_logic:='1';
 begin
  clk<='0';
  wait for PER/2;
  clktmp:=not clktmp;
  clk<=clktmp;
  wait for PER/2;
 end process;

 stimulus:process
 constant PER: time:=40 ns;
 variable tmpreg: std_logic_vector(7 downto 0);
 begin
  reset<='1';
  wait for PER;
  reset<='0';
  load<='0';
  wait for PER;
  din<=(others=>'1');
  wait for PER;

  load<='1';
  din<=(others=>'1');
  tmpreg:="11111111";
  assert(dout=not(tmpreg))
  report "Test Failed..." severity ERROR;
  wait;
 end process;



Tue, 22 Jan 2002 03:00:00 GMT  
 testbench.
Azhar,

I am guessing that your clock process is not doing what you want. This
generates a clock with a 25% duty cycle and a period of 80ns. Try
simplifying it:

clock: process
  constant PER: time := 40 ns;
begin
  clk <= '0';
  wait for PER/2;
  clk <= '1';
  wait for PER/2;
end process;

In the stimulus process, wait for the clock to transition, rather than
waiting for the same amount of time. So rather than "wait for PER" you can
"wait until (clk'event and clk='1')". This will guarantee that the clock
does not occur at the same instant as your other stimulus.

Stephen
--------------------------------------------
Stephen Fraleigh
Ericsson, Inc.
Research Triangle Park, NC


Phone:  (919)472-6877
Fax:    (919)472-7451
--------------------------------------------

Quote:

> Below is the part of my testbench. It is getting compiled but simulation
> runs are not correct. Can somebody help me. Thanks,
> -----------

> clock: process
>  constant PER: time:=40 ns;
>  variable clktmp: std_logic:='1';
>  begin
>   clk<='0';
>   wait for PER/2;
>   clktmp:=not clktmp;
>   clk<=clktmp;
>   wait for PER/2;
>  end process;

>  stimulus:process
>  constant PER: time:=40 ns;
>  variable tmpreg: std_logic_vector(7 downto 0);
>  begin
>   reset<='1';
>   wait for PER;
>   reset<='0';
>   load<='0';
>   wait for PER;
>   din<=(others=>'1');
>   wait for PER;

>   load<='1';
>   din<=(others=>'1');
>   tmpreg:="11111111";
>   assert(dout=not(tmpreg))
>   report "Test Failed..." severity ERROR;
>   wait;
>  end process;



Tue, 22 Jan 2002 03:00:00 GMT  
 testbench.
Hi Stephen Fraleigh,
Thank you very much. I will let you if I need further help. Best regards,

Azhar


Quote:
> Azhar,

> I am guessing that your clock process is not doing what you want. This
> generates a clock with a 25% duty cycle and a period of 80ns. Try
> simplifying it:

> clock: process
>   constant PER: time := 40 ns;
> begin
>   clk <= '0';
>   wait for PER/2;
>   clk <= '1';
>   wait for PER/2;
> end process;

> In the stimulus process, wait for the clock to transition, rather than
> waiting for the same amount of time. So rather than "wait for PER" you can
> "wait until (clk'event and clk='1')". This will guarantee that the clock
> does not occur at the same instant as your other stimulus.

> Stephen
> --------------------------------------------
> Stephen Fraleigh
> Ericsson, Inc.
> Research Triangle Park, NC


> Phone:  (919)472-6877
> Fax:    (919)472-7451
> --------------------------------------------


> > Below is the part of my testbench. It is getting compiled but simulation
> > runs are not correct. Can somebody help me. Thanks,
> > -----------

> > clock: process
> >  constant PER: time:=40 ns;
> >  variable clktmp: std_logic:='1';
> >  begin
> >   clk<='0';
> >   wait for PER/2;
> >   clktmp:=not clktmp;
> >   clk<=clktmp;
> >   wait for PER/2;
> >  end process;

> >  stimulus:process
> >  constant PER: time:=40 ns;
> >  variable tmpreg: std_logic_vector(7 downto 0);
> >  begin
> >   reset<='1';
> >   wait for PER;
> >   reset<='0';
> >   load<='0';
> >   wait for PER;
> >   din<=(others=>'1');
> >   wait for PER;

> >   load<='1';
> >   din<=(others=>'1');
> >   tmpreg:="11111111";
> >   assert(dout=not(tmpreg))
> >   report "Test Failed..." severity ERROR;
> >   wait;
> >  end process;



Wed, 23 Jan 2002 03:00:00 GMT  
 testbench.
You main problem is that your clock and
control and data signals events occur at the SAME delta time.  
CLK changes after ONE delta time after PER/2, and rising edge occurs after 1
delta time after period.
Your reset, load, and and DIn after ONE delta time after period.    Real
circuits don't work that way.  Your solutions:
1. Change the clock as follows:
 signal CLK : std_logic := '1'; -- must initialize.
...
begin
  -- concurrent signal assignment -- simpler
  -- and no delta time.
  CLK <= not CLK after PER/2;
2. Change your stimulus to wait until CLK ='1' instead of waiting for PER.
This insures that all signal assignments thereafter occur in one delta time
after the clk.  Thus;
 stimulus:process
 constant PER: time:=40 ns;
 variable tmpreg: std_logic_vector(7 downto 0);
 begin
  reset<='1';
  wait until Clk '1'; -- for PER;
  reset<='0';
  load<='0';
  wait  until Clk '1'; --  for PER;
  din<=(others=>'1');
  wait  until Clk '1'; -- for PER;

  load<='1';
  din<=(others=>'1');
  tmpreg:="11111111";
  assert(dout=not(tmpreg))
  report "Test Failed..." severity ERROR;
  wait;
 end process;

Checkout my Coding Style book that discusses various testbench design
techniques, including the client/server approach that proved very beneficial in
terms of flexibility, and separation between transactions and protocol.  TOC is
at my web site.
----------------------------------------------------------

-- ** "VHDL Coding Styles and Methodologies, 2nd Edition", Ben Cohen,
--     ISBN 0-7923-8474-1 Kluwer Academic Publishers, 1999
-- ** "VHDL Answers to Frequently Asked Questions, 2nd Edition",
--     Ben Cohen, ISBN 0-7923-8115-7 Kluwer Academic Publishers, 1998
--  Web page:   http://members.aol.com/vhdlcohen/vhdl

<<Below is the part of my testbench. It is getting compiled but simulation
runs are not correct. Can somebody help me. Thanks,
-----------

clock: process
 constant PER: time:=40 ns;
 variable clktmp: std_logic:='1';
 begin
  clk<='0';
  wait for PER/2;
  clktmp:=not clktmp;
  clk<=clktmp;
  wait for PER/2;
 end process;

  stimulus:process
 constant PER: time:=40 ns;
 variable tmpreg: std_logic_vector(7 downto 0);
 begin
  reset<='1';
  wait for PER;
  reset<='0';
  load<='0';
  wait for PER;
  din<=(others=>'1');
  wait for PER;

  load<='1';
  din<=(others=>'1');
  tmpreg:="11111111";
  assert(dout=not(tmpreg))
  report "Test Failed..." severity ERROR;
  wait;
 end process;>>



Wed, 23 Jan 2002 03:00:00 GMT  
 testbench.
Thank you very much, for your help. Yes I really need a book for testbench
deisgn. I have the VHDL primer but it is not sufficient. Does your book
contains lots of example for designing test benches?

Regards,
Azhar


Quote:
> You main problem is that your clock and
> control and data signals events occur at the SAME delta time.
> CLK changes after ONE delta time after PER/2, and rising edge occurs after
1
> delta time after period.
> Your reset, load, and and DIn after ONE delta time after period.    Real
> circuits don't work that way.  Your solutions:
> 1. Change the clock as follows:
>  signal CLK : std_logic := '1'; -- must initialize.
> ...
> begin
>   -- concurrent signal assignment -- simpler
>   -- and no delta time.
>   CLK <= not CLK after PER/2;
> 2. Change your stimulus to wait until CLK ='1' instead of waiting for PER.
> This insures that all signal assignments thereafter occur in one delta
time
> after the clk.  Thus;
>  stimulus:process
>  constant PER: time:=40 ns;
>  variable tmpreg: std_logic_vector(7 downto 0);
>  begin
>   reset<='1';
>   wait until Clk '1'; -- for PER;
>   reset<='0';
>   load<='0';
>   wait  until Clk '1'; --  for PER;
>   din<=(others=>'1');
>   wait  until Clk '1'; -- for PER;

>   load<='1';
>   din<=(others=>'1');
>   tmpreg:="11111111";
>   assert(dout=not(tmpreg))
>   report "Test Failed..." severity ERROR;
>   wait;
>  end process;

> Checkout my Coding Style book that discusses various testbench design
> techniques, including the client/server approach that proved very
beneficial in
> terms of flexibility, and separation between transactions and protocol.
TOC is
> at my web site.
> ----------------------------------------------------------

> -- ** "VHDL Coding Styles and Methodologies, 2nd Edition", Ben Cohen,
> --     ISBN 0-7923-8474-1 Kluwer Academic Publishers, 1999
> -- ** "VHDL Answers to Frequently Asked Questions, 2nd Edition",
> --     Ben Cohen, ISBN 0-7923-8115-7 Kluwer Academic Publishers, 1998
> --  Web page:   http://members.aol.com/vhdlcohen/vhdl

> <<Below is the part of my testbench. It is getting compiled but simulation
> runs are not correct. Can somebody help me. Thanks,
> -----------

> clock: process
>  constant PER: time:=40 ns;
>  variable clktmp: std_logic:='1';
>  begin
>   clk<='0';
>   wait for PER/2;
>   clktmp:=not clktmp;
>   clk<=clktmp;
>   wait for PER/2;
>  end process;

>   stimulus:process
>  constant PER: time:=40 ns;
>  variable tmpreg: std_logic_vector(7 downto 0);
>  begin
>   reset<='1';
>   wait for PER;
>   reset<='0';
>   load<='0';
>   wait for PER;
>   din<=(others=>'1');
>   wait for PER;

>   load<='1';
>   din<=(others=>'1');
>   tmpreg:="11111111";
>   assert(dout=not(tmpreg))
>   report "Test Failed..." severity ERROR;
>   wait;
>  end process;>>



Thu, 24 Jan 2002 03:00:00 GMT  
 testbench.
<<Thank you very much, for your help. Yes I really need a book for testbench
design. I have the VHDL primer but it is not sufficient. Does your book
contains lots of example for designing test benches?>

Yes.   In chapter 11 of the book "VHDL Coding Styles and Methodologies, 2nd
Edition"  I discuss the following:
1. Testbench design methodology
   (validation plan, what's in a TB (clock, BFMs, Verifier, Unit under test)
2. For Bus Functional Models I describe the follwing methods:
  - Waveform generation (similar to what you used)
 - Client/server with VHDL stimulus generation, Text command files, and binary
command files.
I use a memory as my unit under test because it has READ and WRITE
transactions, and most people are familiar with the requirements.  I definitely
use complete working examples (with compilation scripts)  to demonstrate all
the concepts described above.  
 In chapter 12 of same book I describe the UART design and testbench model,
including a verifier to test the UART design.

----------------------------------------------------------

-- ** "VHDL Coding Styles and Methodologies, 2nd Edition", Ben Cohen,
--     ISBN 0-7923-8474-1 Kluwer Academic Publishers, 1999
-- ** "VHDL Answers to Frequently Asked Questions, 2nd Edition",
--     Ben Cohen, ISBN 0-7923-8115-7 Kluwer Academic Publishers, 1998
--  Web page:   http://members.aol.com/vhdlcohen/vhdl



Thu, 24 Jan 2002 03:00:00 GMT  
 testbench.


Quote:
>Azhar,

>I am guessing that your clock process is not doing what you want. This
>generates a clock with a 25% duty cycle and a period of 80ns. Try
>simplifying it:

>clock: process
>  constant PER: time := 40 ns;
>begin
>  clk <= '0';
>  wait for PER/2;
>  clk <= '1';
>  wait for PER/2;
>end process;

>In the stimulus process, wait for the clock to transition, rather than
>waiting for the same amount of time. So rather than "wait for PER" you can
>"wait until (clk'event and clk='1')". This will guarantee that the clock
>does not occur at the same instant as your other stimulus.

>Stephen
>--------------------------------------------
>Stephen Fraleigh
>Ericsson, Inc.
>Research Triangle Park, NC


>Phone:  (919)472-6877
>Fax:    (919)472-7451
>--------------------------------------------


>> Below is the part of my testbench. It is getting compiled but simulation
>> runs are not correct. Can somebody help me. Thanks,
>> -----------

>> clock: process
>>  constant PER: time:=40 ns;
>>  variable clktmp: std_logic:='1';
>>  begin
>>   clk<='0';
>>   wait for PER/2;
>>   clktmp:=not clktmp;
>>   clk<=clktmp;
>>   wait for PER/2;
>>  end process;

>>  stimulus:process
>>  constant PER: time:=40 ns;
>>  variable tmpreg: std_logic_vector(7 downto 0);
>>  begin
>>   reset<='1';
>>   wait for PER;
>>   reset<='0';
>>   load<='0';
>>   wait for PER;
>>   din<=(others=>'1');
>>   wait for PER;

>>   load<='1';
>>   din<=(others=>'1');
>>   tmpreg:="11111111";
>>   assert(dout=not(tmpreg))

Also here ^^^^^^^^ you are testing dout straight after assigning din and
load. You need to allow time for the value of dout to become assigned
(either due to functional delays in your model under test, or due to
delta delays). If there are only delta delays, you could use

wait for 0 ns;
assert dout=not(tmpreg)) ...

Otherwise you need to wait long enough for outputs to settle, e.g.
wait for 20 ns; -- or whatever
assert ...

kind regards

Alan
--
Alan Fitch
DOULOS Ltd.
        Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK

Fax: +44 (0)1425 471 573            
**               Visit THE WINNING EDGE  www.doulos.com               **



Fri, 25 Jan 2002 03:00:00 GMT  
 
 [ 7 post ] 

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