VHDL conversions 
Author Message
 VHDL conversions

I am trying to add some logic vectors of a new type I have created like
so:

library IEEE;
use IEEE.std_logic_1164.all;

Package values is
   subtype LONG is std_logic_Vector (31 downto 0);
   type LONGX2  is array ( 1 downto 0) of LONG;
   type LONGX64 is array (63 downto 0) of LONGX2;
   constant Mask1: std_logic_vector(31 downto 0) :=
"00000000111111111000000000000000";
   constant Mask2: std_logic_vector(31 downto 0) :=
"00000000000000000111111111000000";
end values;

-----------
Then I am trying to add them like so:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use STD.TEXTIO.ALL;
use work.values.all;

entity best is
 port (  clk: in STD_LOGIC;
         path: out LONGX64
       );
end best;

architecture best of best is
begin
   process(clk)
   begin
    for chaz in 0 to 63 loop
        path(chaz)(1) <= "00000000000000001111111111111111";
    end loop;
for chaz in 0 to 63 loop

  path(chaz)(1)<=   to_stdlogicvector(to_bitvector(path(chaz)(1)(7
downto 0) & "000000000000000000000000") + to_bitvector(path(chaz)(1)(23
downto 0) &       "00000000"  and Mask1 ) +  to_bitvector("00000000" &
(path(chaz)(1)(31 downto 24) and Mask2) + to_bitvector("00000000" &
path(chaz)(1)(31 downto 24)));

  path(chaz)(1) <=
to_stdlogicvector(to_bitvector("00000000111111111111111101000000"));

    end loop;
end process;
end best;

---------

I am compiling it with synopsys vhdlan compiler.   I get the following
error:

**Warning:  SEC-6:
 License for 'HDL-Compiler' has expired.
 WARNING: Default changed to compiled engine. See release notes.

**Warning:  SEC-6:
 License for 'HDL-Compiler' has expired.
  path(chaz)(1)<=   to_stdlogicvector(to_bitvector(path(chaz)(1)(7
downto 0) & "000000000000000000000000") + to_bitvector(path(chaz)(1)(23
downto 0) & "00000000"  and Mask1 ) +  to_bitvector("00000000" &
(path(chaz)(1)(31 downto 24) and Mask2) + to_bitvector("00000000" &
path(chaz)(1)(31 downto 24)));

^
**Error: vhdlan,1081 temp.vhd(43):
    Syntax error.
"temp.vhd": errors: 1; warnings: 0.

What is going on?

Help!!!!!!!!!!!!

Salman



Tue, 22 Jan 2002 03:00:00 GMT  
 VHDL conversions
Hallo Salman,

there's a number of problems with your code.

1) the brackets don't match. This is probably the main reason for the
error. According to my count, you need about 4 more closing brackets (I
think!).

2) if you use std_logic_arith for arithmetic, you should do arithmetic
on types SIGNED and UNSIGNED, which are declared in the std_logic_arith
package.

3) If you make two assignments in a process one after another to the
same signal (as you've done), the events created by the first assignment
are deleted by the second assignment (inertial delay). So effectively
the last assignment in the process takes precedence (what we sometimes
call "the last assignment wins" on our courses). So only the assignment

Quote:
>  path(chaz)(1) <=
>to_stdlogicvector(to_bitvector("00000000111111111111111101000000"));

has any effect in your code - all the additions you are attempting to do
will have no effect.

4) Your process is sensitive to clk. This means it will execute on both
positive and negative edges (in fact when there is any change of value
on clk). Most (probably all?) synthesis tools will not accept this. If
you want positive edge clocking, you can use

process
begin
  wait until clk = '1';

....

end process;

5) Finally, all signal assignments "<=" schedule events in the future.
So your first loop will not have come into effect by the time your
second loop operates, because the process has not yet suspended - you
will pick up the "current" values of path(chaz)(1), not the value you
tried to initialize it to  in the first loop. If you want to read a
value you have just assigned, the object assigned to should be a
variable.

kind regards,

Alan

P.S From your code, I would suggest you start with a simpler example
first, e.g. just adding two vectors. You can then extend it to add your
array of arrays later.



Quote:
>I am trying to add some logic vectors of a new type I have created like
>so:

>library IEEE;
>use IEEE.std_logic_1164.all;

>Package values is
>   subtype LONG is std_logic_Vector (31 downto 0);
>   type LONGX2  is array ( 1 downto 0) of LONG;
>   type LONGX64 is array (63 downto 0) of LONGX2;
>   constant Mask1: std_logic_vector(31 downto 0) :=
>"00000000111111111000000000000000";
>   constant Mask2: std_logic_vector(31 downto 0) :=
>"00000000000000000111111111000000";
>end values;

>-----------
>Then I am trying to add them like so:

>library IEEE;
>use IEEE.std_logic_1164.all;
>use IEEE.std_logic_arith.all;
>use IEEE.std_logic_textio.all;
>use STD.TEXTIO.ALL;
>use work.values.all;

>entity best is
> port (  clk: in STD_LOGIC;
>         path: out LONGX64
>       );
>end best;

>architecture best of best is
>begin
>   process(clk)
>   begin
>    for chaz in 0 to 63 loop
>        path(chaz)(1) <= "00000000000000001111111111111111";
>    end loop;
>for chaz in 0 to 63 loop

>  path(chaz)(1)<=   to_stdlogicvector(to_bitvector(path(chaz)(1)(7
>downto 0) & "000000000000000000000000") + to_bitvector(path(chaz)(1)(23
>downto 0) &       "00000000"  and Mask1 ) +  to_bitvector("00000000" &
>(path(chaz)(1)(31 downto 24) and Mask2) + to_bitvector("00000000" &
>path(chaz)(1)(31 downto 24)));

>  path(chaz)(1) <=
>to_stdlogicvector(to_bitvector("00000000111111111111111101000000"));

>    end loop;
>end process;
>end best;

>---------

>I am compiling it with synopsys vhdlan compiler.   I get the following
>error:

>**Warning:  SEC-6:
> License for 'HDL-Compiler' has expired.
> WARNING: Default changed to compiled engine. See release notes.

>**Warning:  SEC-6:
> License for 'HDL-Compiler' has expired.
>  path(chaz)(1)<=   to_stdlogicvector(to_bitvector(path(chaz)(1)(7
>downto 0) & "000000000000000000000000") + to_bitvector(path(chaz)(1)(23
>downto 0) & "00000000"  and Mask1 ) +  to_bitvector("00000000" &
>(path(chaz)(1)(31 downto 24) and Mask2) + to_bitvector("00000000" &
>path(chaz)(1)(31 downto 24)));

>^
>**Error: vhdlan,1081 temp.vhd(43):
>    Syntax error.
>"temp.vhd": errors: 1; warnings: 0.

>What is going on?

>Help!!!!!!!!!!!!

>Salman

--
Alan Fitch
DOULOS Ltd.
        Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK

Fax: +44 (0)1425 471 573            
**               Visit THE WINNING EDGE  www.doulos.com               **


Tue, 22 Jan 2002 03:00:00 GMT  
 VHDL conversions

Quote:

> I am trying to add some logic vectors of a new type I have created like
> so:

<cut code>

Quote:
> **Warning:  SEC-6:
>  License for 'HDL-Compiler' has expired.
>   path(chaz)(1)<=   to_stdlogicvector(to_bitvector(path(chaz)(1)(7
> downto 0) & "000000000000000000000000") + to_bitvector(path(chaz)(1)(23
> downto 0) & "00000000"  and Mask1 ) +  to_bitvector("00000000" &
> (path(chaz)(1)(31 downto 24) and Mask2) + to_bitvector("00000000" &
> path(chaz)(1)(31 downto 24)));

> ^
> **Error: vhdlan,1081 temp.vhd(43):
>     Syntax error.
> "temp.vhd": errors: 1; warnings: 0.

1: use ieee.std_logic_unsigned arithmetic package to lose all the
    to_stdlogicvector/to_bitvector conversions

2: path is an output port - you can't read it's value internally - use
    an internal signal or variable

3. you're assigning to path(chaz)(1) twice inside the loop - the second
assignment
   overwrites the first - assume the second is an error...

4. Get a new license for synopsys  =:^)

Below compiles OK, but you'd need to check it functionally....

B

------------------------------------------------------
Esperan Ltd
The world's leading HDL and FPGA training company
www.esperan.com
------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

Package values is
   subtype LONG is std_logic_Vector (31 downto 0);
   type LONGX2  is array ( 1 downto 0) of LONG;
   type LONGX64 is array (63 downto 0) of LONGX2;
   constant Mask1: std_logic_vector(31 downto 0) :=
"00000000111111111000000000000000";
   constant Mask2: std_logic_vector(31 downto 0) :=
"00000000000000000111111111000000";
end values;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.values.all;

entity best is
 port (  clk: in STD_LOGIC;
         path_op: out LONGX64
       );
end best;

architecture best of best is
begin
   process(clk)
     variable path : longx64;
   begin
    for chaz in 0 to 63 loop
        path(chaz)(1) := "00000000000000001111111111111111";
    end loop;
for chaz in 0 to 63 loop

  path(chaz)(1):=
                  (path(chaz)(1)(7 downto 0) & "000000000000000000000000")
                + ((path(chaz)(1)(23 downto 0) & "00000000")   and Mask1 )
                + ("00000000" & (path(chaz)(1)(31 downto 24)  and Mask2))
                + ("00000000" & path(chaz)(1)(31 downto 24));

  --path(chaz)(1) <= "00000000111111111111111101000000";

    end loop;
  path_op <= path;
end process;
end best;



Tue, 22 Jan 2002 03:00:00 GMT  
 VHDL conversions

Quote:

> 1: use ieee.std_logic_unsigned arithmetic package to lose all the
>     to_stdlogicvector/to_bitvector conversions

You did mean IEEE.numeric_std, didn't you? Otherwise, this is
very bad advice as the vhdl FAQ clearly explains.

--
Jan Decaluwe           Easics              
Design Manager         System-on-Chip design services  
+32-16-395 600         Interleuvenlaan 86, B-3001 Leuven, Belgium



Fri, 25 Jan 2002 03:00:00 GMT  
 VHDL conversions

Is there anyone knows how to write VHDL/Verilog
implementation of B-tree algorithm. Would appreciate
very much if you do so and let me know how to do so.

Thanks in advance.

Tassi.

Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.



Sun, 27 Jan 2002 03:00:00 GMT  
 
 [ 6 post ] 

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