testing methods, BIST 
Author Message
 testing methods, BIST


>   I search web pages about digital circuits' testing methods, BIST,
> especially about testability analysis and test-point insertion in RTL
> VHDL specifications for scan-based BIST.

The following article might be of interest:

  "Inserting Scan at the Behavi{*filter*}Leve"
  Chouki Aktouf, Hrv Fleury, Chantal Robach
  IEEE Design & Test of Computers, v17n3 (July - Sep. 2000)

Abstract (from http://www.*-*-*.com/ ):

  "This article presents a method for inserting test logic at the
   behavi{*filter*}level of a VHDL design description. The method is easy
   to use, and in most cases it requires lower area overhead than
   classical scan insertion methods."

Simon Brady                                            sjbrady
Research Assistant, Computer Science Dept.               at
University of Otago, Dunedin, New Zealand            acm dot org

Thu, 24 Apr 2003 03:00:00 GMT  
 [ 1 post ] 

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