VHDL - directives for synthesize 
Author Message
 VHDL - directives for synthesize

Hi!
Are there any directives in VHDL for synthesize like "'ifdef" in Verilog.
For example when I want synthesize and implement some parts of project could
I set any constants in i.e. package ???
And next, use them as variables for conditional compilation in C or
something like that.

Jurek



Mon, 27 Sep 2004 22:59:35 GMT  
 VHDL - directives for synthesize

Quote:

> Are there any directives in VHDL for synthesize like "'ifdef" in Verilog.
> For example when I want synthesize and implement some parts of project could
> I set any constants in i.e. package ???
> And next, use them as variables for conditional compilation in C or
> something like that.

You can use boolean constants or:
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#cond_compile

-- Mike Treseler



Tue, 28 Sep 2004 01:15:16 GMT  
 
 [ 2 post ] 

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