problem with Valid VHDL. 
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 problem with Valid VHDL.



Sat, 27 Jan 1996 09:32:20 GMT  
 problem with Valid VHDL.

My chef is searching for the following article:

Vanzieloghem, E.:
"VHDL and Synthesis Based ASIC-Design. A Case Study."
in: First European Working Conference on VHDL Methodology.
Merseille, Sept. 1990.

If there is everyone who is able to give me an idea or informations,
where or how I can get it, please contact me.

Thank you.


                Tel:    +49-351-462-2287
                Fax: +49-351-462-2190

Technische Universit?t Dresden
Fakult?t fr Verkehrswissenschaften
Institut fr Verkehrinformationssysteme
Mommsenstr. 13
01069 Dresden
Germany



Sun, 28 Jan 1996 00:41:42 GMT  
 
 [ 3 post ] 

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