In VHDL-AMS Im trying to model a controller for a tank filled with liquid.
Qo is the outgoing flow. The input flow depends on the status of a valve and
is 0.0 or Qmax
The controller keeps the height of the liquid (h) between two levels, using
a hysteresis hhys of 0.1. If the liquid in the tank drops below
hset-hhys(=0.9), the valve is opened. If the liquid in the tank rises above
hset (=1.0) the valve is closed. The status of the valve is given using the
signal alpha, which gets his value in the process valve.
The simulation of the following process hangs at time 0.04 sec. (no. Asp=0)
If line X or line Y would be replaced with wait for 5 sec; the process
works correctly. So it seems that no more then one wait until habove(E)
statement is possible.

Is the written model illegal VHDL or is it something else?

Thanks already,

Ramon

ENTITY fill IS
END ENTITY fill;

ARCHITECTURE behav OF fill IS

    QUANTITY h        : real;
    QUANTITY Qo     :  real;
    signal alpha          : real := 1.0;
    constant A             : real := 10.0;
    CONSTANT h0      : real := 0.1;
    CONSTANT hset   : real := 1.0;
    CONSTANT hhys   : real := 0.1;
    CONSTANT k        : real := 0.5;
    CONSTANT Qmax : real := 1.0;

BEGIN

break h=>0.1;

Qo==k * sqrt(h);
h'dot==((alpha * Qmax) - (Qo))/A;

break on alpha;

valve: process
begin
alpha<=1.0;
wait until h'above(1.0);        --[line X]
alpha<=0.0;
wait until not(h'above(0.9)); --[line Y]

end process valve;

END ARCHITECTURE behav;

Hi,

This appears to be legal VHDL-AMS. However, you may be asking the
impossible (at least given the current state of the art)! You are
changing the value of alpha, according to h. Therefore h'dot is
discontinuous. The break on alpha; statement should cause the simulator
to stop and reinitialise when alpha changes. Ideally, therefore, there
should be no problem.

BUT, both the existing VHDL-AMS simulators of which I am aware are based
on existing march-in-time simulators. The numerical integration methods
weren't designed to be stopped and restarted after discontinuities. The
VHDL-AMS break statement has been fitted on top of these algorithms,
perhaps in a less than perfect manner. I suspect the simulator is
attempting to work its way round the discontinuity by cutting the
timestep. By putting in the "wait for 5 s" statement, you are avoiding
the discontinuity (I think) by putting a delay in the change in alpha
and (I guess, without running the simulation) allowing h'dot to approach
a value where a change in alpha does not cause the discontinuity.

I don't know that there is a simple solution to this problem. You may
have to wait until the tool vendors sort out how to implement a break
correctly!
--
===================================================================
Dr Mark Zwolinski                        Tel. (+44) (0)23 8059 3528  
Dept. of Electronics & Computer Science  Fax. (+44) (0)23 8059 2901

Southampton SO17 1BJ, UK             http://www.ecs.soton.ac.uk/~mz