Funny 
Author Message
 Funny

.....
signal tobe : std_logic;
signal question : std_logic;
....
question<= tobe or not tobe;
....
:)
This is a sample -VHDL mixed with Sheakspeare.

Adam



Fri, 16 Sep 2005 04:59:20 GMT  
 Funny

Quote:

> .....
> signal tobe : std_logic;
> signal question : std_logic;
> ....
> question<= tobe or not tobe;
> ....
> :)
> This is a sample -VHDL mixed with Sheakspeare.

> Adam

How about

t4u     <=   t42 or 240;

pcw



Fri, 16 Sep 2005 13:14:27 GMT  
 Funny

Quote:
> question<= tobe or not tobe;

Not as good as Petter Gustad's Verilog version:

8'h2b | ~8'h2b

(It's not often I prefer Verilog...)
--
Jonathan Bromley, Consultant

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Sat, 17 Sep 2005 00:24:50 GMT  
 
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