alliance VHDL subset. 
Author Message
 alliance VHDL subset.

Hi
is anyone out there using Alliance 2 for Linux...specially the VHDL package.
I have heard that it is a fairly limiting subset of the language, anyone
got any comments on this.
Ian.
--
Ian G. Clark BSc.(ENG) ... (Dr. Wizard), Electronic and Electrical Engineering
Kings College London. (These comments are my own, not from my organisation)



Tue, 04 Mar 1997 21:20:21 GMT  
 alliance VHDL subset.

: Hi
: is anyone out there using Alliance 2 for Linux...specially the VHDL package.
: I have heard that it is a fairly limiting subset of the language, anyone
: got any comments on this.

I see this question here frequently so I looked up the Alliance FAQ and,
essentially it said, "read the man pages".  Well at least it said which
man pages to read.  I am not wise enough to digest the man pages well enough
for you, so instead what I have done below is to (for the most part) copy
them.  I have cut out the examples from the man pages.  There are four
applicable man pages, all four of which are here below.

    man vhdl - gives a general overview of the limits to Alliance VHDL
    man vst  - gives limitations to structural code
    man vbe  - gives limitations to dataflow behavi{*filter*}code
    man fsm  - gives limitations to finite state machine code

This question comes up so frequently that it probably would be a good idea
if some smart person (!I) would abstract this info and put it into the
FAQ for this news group.

VHDL(5)         VHDL subset of MASI/CAO-VLSI lab.         VHDL(5)

NAME
     vhdl
     ALLIANCE VHDL subset.

ORIGIN
     ALLIANCE CAD system from the CAO-VLSI team at MASI labora-
     tory, University P. et M. Curie
     4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE

DESCRIPTION
     The ALLIANCE VHDL subset is dedicated to digital synchronous
     circuits design.  The same subset is used for:
          logic simulation (asimut)
          logic synthesis (logic)
          functionnal abstraction (desb)
          formal proof (proof)

     The ALLIANCE VHDL subset is fully compatible with the IEEE
     VHDL standard Ref.  1076 (1987). That means that a VHDL
     description using the ALLIANCE subset can be simulated with
     any full-VHDL commercial compiler-simulator.

     Here follows the main restrictions of the ALLIANCE subset.

     The VHDL description of a circuit is made of two seperate
     parts: the external view and the internal view.

     The external view defines the name of the circuit and its
     interface. The interface of a circuit is a list of ports.
     Each port is specified by its name, its mode, its type, its
     constraint for an array and, its kind.

     The mode of a port depends only on the manner the port is
     used inside the circuit (in the internal view of the cir-
     cuit). If the value of a port is to be read in the view of
     the description, the port must be declared with the mode in.
     If the value of a port is to be written by the internal
     view, the port must be declared with the mode out. If both
     above conditions are satisfied the port must be declared
     with the mode inout.

     Only structural and behavioural data flow are supported as
     internal view.

     In order to allow automatic translation from structural VHDL
     to other netlist formats (EDIF, ALLIANCE, COMPASS, ...) it
     is not possible to mix behavioural and structural descrip-
     tion. Of course, a circuit, a subcircuit or a cell can have
     two different descriptions:
          a structural view may be defined in a file with a .vst
          extension (see vst(5)).
          a behavioural data flow description may be defined in a
          file with a .vbe extension (see vbe(5)).

     A typical VHDL model will be made of a hierarcical struc-
     tural description (a hierarchy of structural files) and, for
     each leaf cell, a behavioural description.

     In a behavioural description, only concurrent statements
     (except process) are supported. Up to now, sequential state-
     ments are not allowed by the ALLIANCE VHDL compiler.

     As behavioural descriptions are used for both logic simula-
     tion and logic synthesis, detailed timing information is not
     needed. That means, within a concurrent statement no delay
     can be specified (after is not supported).

     A predefined set of types has been defined (other user
     defined types are not supported):

     bit            the predefined standard bit type ('0' or '1')

     bit_vector     array of bit

     mux_bit        a resolved subtype of bit using the mux reso-
                    lution function. This function checks that
                    only one driver is actually connected to a
                    signal. The effective value of the signal is
                    the value of the active driver. If all
                    drivers are disconnected, the value of the
                    signal is '1' (pull up). A signal of type
                    mux_bit must be declared with the kind bus.

     mux_vector     array of mux_bit

     wor_bit        a resolved subtype of bit using the wor reso-
                    lution function. This function allows a sig-
                    nal be driven by more than one driver. All
                    active drivers have to drive the same value.
                    The effective value of the signal is the
                    value of active drivers. If all drivers are
                    disconnected, the value of the signal is '1'
                    (pull up). A signal of type wor_bit must be
                    declared with the kind bus.

     wor_vector     array of wor_bit

     reg_bit        a resolved subtype of bit using the reg reso-
                    lution function. This function checks that
                    only one driver is actually connected to a
                    signal. The effective value of the signal is
                    the value of the active driver. A signal of
                    type reg_bit must be declared with the kind
                    register (which makes the signal keep its
                    previous value when all drivers are discon-
                    nected).

     reg_vector     array of reg_bit

     In the next ALLIANCE release the VHDL subset will be largely
     extended (sequential statements, user defined types) .

VST(5)          VHDL subset of MASI/CAO-VLSI lab.          VST(5)

NAME
     vst
     VHDL structural subset.

DESCRIPTION
     This document describes the ALLIANCE VHDL subset for struc-
     tural descriptions.

     The declaration part of a structural description includes
     signal decalarations and component declarations.

     An internal signal can be declared of any type supported by
     the present VHDL subset except reg_bit and reg_vector.

     A component must be declared with exactly the same port
     description as in its entity specification. This means that
     local ports are to be declared with the same name, type and
     kind and in the same order.

     A structural description is a set of component instanciation
     statements.  Instances' ports are connected to each other
     trough signals in a port map specification. Both explicit
     and implicit port map specifications are supported by the
     ALLIANCE VHDL subset.

     The present version of the VHDL compiler does not allow
     unconnected ports (the open mode is not supported).

     Only the concatenation operator (&) can be used in the
     actual part (effective signal conntected to a formal port)
     of a port map specification.

VBE(5)          VHDL subset of MASI/CAO-VLSI lab.          VBE(5)

NAME
     vbe
     VHDL behavioural subset.

DESCRIPTION
     This document describes the ALLIANCE VHDL subset for
     behavioural data flow descriptions.

     CONCURRENT STATEMENTS
     In a data flow architecture only concurrent statements
     (except process) are supported. All sequential statements
     including loops, signal assignment, etc .. are to be ban-
     ished.

     Allowed conncurrent statements are:
          simple signal assignment
          conditional signal assignment
          selected signal assignment
          concurrent assert statement
          block statement

     BUSES
     When using concurrent statements, an ordinary signal can be
     assigned only once.  The value of the signal must be expli-
     citly defined by the signal assignment (for example, in a
     selected signal assignment the value of the target signal is
     to be defined for every value that the select expression can
     take).

     The above constraint may be felt as a hard restriction when
     designing distributed controled hardware (precharged line,
     distributed multiplexer, etc ...). To hurdle this, VHDL uses
     a special feature: guarded-resolved signals.

     A resolved signal is a signal declared with a resolved sub-
     type (see vhdl(5)). A resolved subtype is a type combined
     with a resolution function. A resolved signal can be
     assigned by multiple signal assignments. Depending on the
     value of each driver, the resolution function determines the
     effective value of the signal.

     A guarded signal is a resolved signal with drivers that can
     be disconntected.  A guarded signal must be assigned inside
     a block statement through a guarded signal assignment.

     A distributed multiplexer may be described as :

     signal Distributed_Mux : mux_bit bus;
     begin
     first_driver_of_mux : block (Sel1 = '1')
     begin
       Distributed_Mux <= guarded Data1;
     end block;

     second_driver_of_mux : block (Sel2 = '1')
     begin
       Distributed_Mux <= guarded Data2;
     end block;

     LATCHES and REGISTERS
     Sequential elements must be explicitly declared using the
     type reg_bit or reg_vector (and must be of kind register). A
     sequential element must be assigned inside a block statement
     by a guarded signal assignment.

     Falling edge triggered D flip flop :

     signal Reg : reg_bit register;
     begin
     flip_flop : block (ck = '0' and not ck'STABLE)
     begin
       Reg <= guarded Din;
     end block;

     Level sensitive latch:

     signal Reg : reg_bit
...

read more »



Thu, 13 Mar 1997 06:08:18 GMT  
 
 [ 2 post ] 

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