looking for VHDL to verilog translator 
Author Message
 looking for VHDL to verilog translator

Hi, I running a VHDL simulation using Synopsys and also have
a set of VHDL library elements.  I would like to port my library
elements to verilog for use on another verilog based design
effort and don't want to convert them by hand.  Does anyone
know a way to translate the library elements from VHDL to
verilog.  You could almost write a script to do it since its
very low-level VHDL.  I just don't have the time or script
expertise and wanted to find an easier path.

Please respond to my email address if possible!

Thanks

Jim McGrath



Fri, 08 May 1998 03:00:00 GMT  
 looking for VHDL to verilog translator

Quote:

>Hi, I running a VHDL simulation using Synopsys and also have
>a set of VHDL library elements.  I would like to port my library
>elements to verilog for use on another verilog based design
>effort and don't want to convert them by hand.  Does anyone
>know a way to translate the library elements from VHDL to
>verilog.  You could almost write a script to do it since its
>very low-level VHDL.  I just don't have the time or script
>expertise and wanted to find an easier path.

>Please respond to my email address if possible!

>Thanks

>Jim McGrath

Check out ASC's translation aid, VHDL2verilog, at http://www.ascinc.com

--
*       Sashi Obilisetty                                                        *
*       Alternative System Concepts, Inc.                                       *
*       PO Box 128 Windham NH 03087                                             *
*       tel (603) 437-2234 fax (603) 437-ASC2   URL http://www.ascinc.com     *



Sat, 09 May 1998 03:00:00 GMT  
 
 [ 2 post ] 

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