AZ-PHZ Principal Engineer ASIC/FPGA Design in VHDL/Verilog 
Author Message
 AZ-PHZ Principal Engineer ASIC/FPGA Design in VHDL/Verilog

This is a leading position in which you report to the director of
Engineering for an up and coming company. You would be
the main player and supervisor for this Phoenix based company. Please email
me your resume. If you know someone
interested in this job please forward it on to the right person. This is an
amazing opportunity.

Principal Engineer ASIC Design
Education:
BS/MS in Electrical or Computer Engineering
10+ years experience
Responsibilities:
Project technical guidance and leadership
Digital system architecture development & partitioning
HW vs. SW partitioning
Digital subsystem/ASIC/FPGA detailed logic design
Synthesizable VHDL/Verilog model design
Scripts and utilities development
Provide sales support
Write proposals
Manage projects on time and budget schedules
Desired Skills:
Ability to express logic in synthesizable VHDL or verilog
Firm understanding of the transformation of RTL code into gates
ASIC or FPGA design experience
Project planning and leadership experience
Understanding of high-speed and sub-micron design issues
Excellent analytical and communication skills
Highly motivated self starter, well organized
Solaris or Windows-NT
Preferred:
BIST
Test complier
Fault Grading
Test generation
Firmware / Assembly
CMDA / TDMA
Digital PLL design
Clock tree Design
DMA design
1394
802.3
FIFO design
Bus interface design
Datapump design

Quote:
>100k gates

Sub-miron experience
FPGA - Xilina or Altera
Required tool experience
Synopses design Complier
VHDL simulation (Modelsim, Speedwave) or
Verilog simulation (Chronologic, Cadence)
Preferred:
C++,Perl, TCL/tk, Logic Analyzers,ICE, DSO, Performace Analyers,
Viewlog, Mentor Graphics


Mon, 25 Aug 2003 03:36:16 GMT  
 
 [ 1 post ] 

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