My code in a xi 4000 FPGA has to listen to 2 reset signals (1 coming
from a power on and one coming from a vmebus).

Reset_N <= '0' when (Reset_pow = '0' or Sysres = '0')

In the toplevel I or the 2 reset signals (not in a clocked process so
just asynchronous).  The result of this or function is then
distributed towards several VHDL blocks of the with classic structure:

somewhere in toplevel:

    Reset_N <= '0' when (Reset_pow = '0' or Sysres = '0')

some block where it is distributed to:

    process(Clock, Reset_N)
    begin
    if (Reset_N = '0') then
       ...
    elsif(Clock'event and Clock = '1') then
       ...
    end if;
    end process;

This compiles with foundation and runs without problem BUT:

In some systems there is a very slow Reset and it seems this creates
sometimes a metastable, uhm, something ...

To overcome this I want to put 1 or more flip flops to the Reset_N
signal so I tried the following in the top level:

    Reset_N_INTERMEDIATE <= '0' when (Reset_pow = '0' or Sysres = '0')

And then I add extra process to top level:

    process(Clock, Reset_N_INTERMEDIATE)
    begin
    if(Reset_N_INTERMEDIATE = '0') then
      Reset_N <= '0';
    elsif(Clock'event and Clock = '1') then
      Reset_N <= Reset_N_INTERMEDIATE;
    end if;

    end process;

And now Foundation just doesn't want to take it, it gives pages of
warnings with things like

warning Reset_pow does not set/reset ...
warning Sysres does not set/reset ...

all together with the flip flop latch warnings

What can I do?

elsif(Clock'event and Clock = '1') then
:       Reset_N <= Reset_N_INTERMEDIATE;

into

elsif(Clock'event and Clock = '1') then
:       Reset_N <= '1';

also, I wouldn't clock the reset signal at all. Instead, I would
replace a simple buffer after the ORing of the individual resets.
Reset-lines are often dedicated lines and may not be synchronized
inside the chip (don't know about X4000-series) Also
you may need some sort of flickering filter inside or outside the
chip, if that is causing the problem.

regards,
juza

: My code in a xi 4000 FPGA has to listen to 2 reset signals (1 coming
: from a power on and one coming from a vmebus).

: Reset_N <= '0' when (Reset_pow = '0' or Sysres = '0')

: In the toplevel I or the 2 reset signals (not in a clocked process so
: just asynchronous).  The result of this or function is then
: distributed towards several VHDL blocks of the with classic structure:

: somewhere in toplevel:

:     Reset_N <= '0' when (Reset_pow = '0' or Sysres = '0')

: some block where it is distributed to:

:     process(Clock, Reset_N)
:     begin
:     if (Reset_N = '0') then
:        ...
:     elsif(Clock'event and Clock = '1') then
:        ...
:     end if;
:     end process;

: This compiles with foundation and runs without problem BUT:

: In some systems there is a very slow Reset and it seems this creates
: sometimes a metastable, uhm, something ...

: To overcome this I want to put 1 or more flip flops to the Reset_N
: signal so I tried the following in the top level:

:     Reset_N_INTERMEDIATE <= '0' when (Reset_pow = '0' or Sysres = '0')

: And then I add extra process to top level:

:     process(Clock, Reset_N_INTERMEDIATE)
:     begin
:     if(Reset_N_INTERMEDIATE = '0') then
:       Reset_N <= '0';
:     elsif(Clock'event and Clock = '1') then
:       Reset_N <= Reset_N_INTERMEDIATE;
:     end if;

:     end process;

: And now Foundation just doesn't want to take it, it gives pages of
: warnings with things like

: warning Reset_pow does not set/reset ...
: warning Sysres does not set/reset ...

: all together with the flip flop latch warnings

: What can I do?

--
Juza

Dont you mean:

Reset_N <= '0' when (Reset_pow = '0' or Sysres = '0') else
                    '1';

--
Benjamin Todd
European Organisation for Particle Physics
SL SPS/LHC -- Control -- Timing Division
CERN, Geneva, Switzerland,  CH-1211
Building 864 Room 1 - A24

Nope, that line doesn't really bring in much more info. Besides, he
wanted to clock the reset-line...

regards,
juza

: Dont you mean:

: Reset_N <= '0' when (Reset_pow = '0' or Sysres = '0') else

: --
: Benjamin Todd
: European Organisation for Particle Physics
: SL SPS/LHC -- Control -- Timing Division
: CERN, Geneva, Switzerland,  CH-1211
: Building 864 Room 1 - A24

:> Greetings,
:>
:> My code in a xi 4000 FPGA has to listen to 2 reset signals (1 coming
:> from a power on and one coming from a vmebus).
:>
:> Reset_N <= '0' when (Reset_pow = '0' or Sysres = '0')
:>
:> In the toplevel I or the 2 reset signals (not in a clocked process so
:> just asynchronous).  The result of this or function is then
:> distributed towards several VHDL blocks of the with classic structure:
:>
:> somewhere in toplevel:
:>
:>     Reset_N <= '0' when (Reset_pow = '0' or Sysres = '0')
:>
:> some block where it is distributed to:
:>
:>     process(Clock, Reset_N)
:>     begin
:>     if (Reset_N = '0') then
:>        ...
:>     elsif(Clock'event and Clock = '1') then
:>        ...
:>     end if;
:>     end process;
:>
:> This compiles with foundation and runs without problem BUT:
:>
:> In some systems there is a very slow Reset and it seems this creates
:> sometimes a metastable, uhm, something ...
:>
:> To overcome this I want to put 1 or more flip flops to the Reset_N
:> signal so I tried the following in the top level:
:>
:>     Reset_N_INTERMEDIATE <= '0' when (Reset_pow = '0' or Sysres = '0')
:>
:> And then I add extra process to top level:
:>
:>     process(Clock, Reset_N_INTERMEDIATE)
:>     begin
:>     if(Reset_N_INTERMEDIATE = '0') then
:>       Reset_N <= '0';
:>     elsif(Clock'event and Clock = '1') then
:>       Reset_N <= Reset_N_INTERMEDIATE;
:>     end if;
:>
:>     end process;
:>
:>
:> And now Foundation just doesn't want to take it, it gives pages of
:> warnings with things like
:>
:> warning Reset_pow does not set/reset ...
:> warning Sysres does not set/reset ...
:>
:> all together with the flip flop latch warnings
:>
:> What can I do?

--
Juza

process(Clock, Reset_Pow, Sysres)
    begin
    if(Reset_Pow= '0' or Sysres = '0') then
      Reset_N <= '0';
    elsif(Clock'event and Clock = '1') then
      Reset_N <= '1';
    end if;