VHDL plan 
Author Message
 VHDL plan

Just took a quick review of your plan again. At least as it currently
stands
in the /nfs/links/vhdl area. My only question is regarding the VHDL
usage
tool. It is mentioned twice in the plan but never in detail.  My view is
that such a tool has a variety of uses from orienting new developers to
marketing. One could argue that it is the prototype for the VHDL version
of StyleCheck. At any rate it will absorb some development cycles.

I don't know what the current thinking is on such a tool. I proposed
something comparable in the early days of our verilog development.
Nothing came of it,
and I didn't have the time to pursue it.

-m



Sat, 20 May 2000 03:00:00 GMT  
 
 [ 1 post ] 

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