Inout pin 
Author Message
 Inout pin

Dear all
??? Please give me some detial how to use :? INOUT? std_logic ;
I don't understand how to use inout port !!
really!!! need some help



Mon, 20 May 2002 03:00:00 GMT  
 Inout pin

Quote:

>Dear all
> Please give me some detial how to use : INOUT std_logic ;
>I don't understand how to use inout port !!
>really!!! need some help


Hello wannarat,

To use a INOUT port you define the port in the entity declaration as INOUT.
Now you can use the signal on the pin as an input in your architecture. When
you want to use the pin as an output, you switch an output statement from
tri-state ('Z') to the desired output. In the example the dataregister is an
output when the ram is read and an input when the RAM is written.

You have to be carefull to set the output to 'Z' when no output is needed.

entity ram is
port (
  data  : inout std_logic_vector(7 downto 0);
  n_wr  : in  std_logic;
  n_oe  : in  std_logic;
);
end ram;

architecture ram_arch of ram is

begin
signal  dataregister  : std_logic_vector(7 downto 0);

-- -------------------------------------------------------------------------
--
-- Read data from the databus (use data as OUTPUT)
--
read_data: process(n_oe, dataregister)
begin
 if n_oe = '0' then
  data <= dataregister;
 else
  data <= (others => 'Z');
 end if;
end process read_data;

-- -------------------------------------------------------------------------
--
-- Write data to dataregister (use data as INPUT)
--
write_data: process(n_wr)
begin
 if falling_edge(n_wr) then
  dataregister <= data;
 end if;
end process;

end ;

I hope this helps,
Mark.



Mon, 20 May 2002 03:00:00 GMT  
 Inout pin

Quote:


> >Dear all
> > Please give me some detial how to use : INOUT std_logic ;
> >I don't understand how to use inout port !!
> >really!!! need some help

> Hello wannarat,

> To use a INOUT port you define the port in the entity declaration as INOUT.
> Now you can use the signal on the pin as an input in your architecture. When
> you want to use the pin as an output, you switch an output statement from
> tri-state ('Z') to the desired output. In the example the dataregister is an
> output when the ram is read and an input when the RAM is written.

> You have to be carefull to set the output to 'Z' when no output is needed.

At least with Synopsys CARE is to be spelled uppercase.

I had some spare pins at my design (FPGA) which I declared as inout.
When using them as output everything is fine: synopsys notices that
they never go tristate and makes pure output drivers.
However when they are used as inputs you get a problem with simulation.
Since from "inside" the signal is not assigned with a value,
the simulator uses 'U'. Hence inside the circuit this signal stays
"U" all the time.
This can be cured with an assignment 'Z'.
But an unconditional assignment of 'Z' is not synthesizable.
In conclusion: use a pragma:

-- pragma synthesis_off
ldc <= 'Z';
-- pragma synthesis_on

if you use an INOUT-declared signal only as input.
For all other cases the explanation by Mark is just fine.

-----------------------------------------------------------------
                        Andreas C. Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
                        Tel.: +49 451 500-3741, Fax: -3687

                        Home: http://www.iti.mu-luebeck.de/~doering
                             quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------



Mon, 20 May 2002 03:00:00 GMT  
 
 [ 3 post ] 

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