Combining signals as input to a port 
Author Message
 Combining signals as input to a port

Quote:

> Pardon what may be a stupid question, but I'm new to vhdl ...

> Suppose I have a port to a component that is an array, e.g.

> PORT( ...
>       addr : IN std_logic_vector( 2 DOWNTO 0 );
>       ...
>     );

> and I have some individual signals I want to use as the
> input to this port, e.g. a2, a1, a0.

> I tried:

> PORT MAP( ...
>           addr => ( a2 & a1 & a0 );

This is a problem since '( a2 & a1 & a0 )' is a function,
thus it cannot be applied in a port association.  (It
would be acceptable in a function or procedure call.)

Quote:
>           ...
>         );

> but the compiler didn't like it.  All I have been able to
> come up with is:

> PORT MAP( ...
>           addr( 2 ) => a2;
>           addr( 1 ) => a1;
>           addr( 0 ) => a0;
>           ...
>         );

> Surely there's an easier way to do this ...

The only other practical approach is to declare a new
vector signal and use it in the port mapping such as:

signal a_bus:  std_logic_vector(2 downto 0);

a_bus  <=  ( a2 & a1 & a0 );

PORT MAP(...
         addr  =>  a_bus;
         ...

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Tue, 11 Apr 2000 03:00:00 GMT  
 Combining signals as input to a port

Pardon what may be a stupid question, but I'm new to vhdl ...

Suppose I have a port to a component that is an array, e.g.

PORT( ...
      addr : IN std_logic_vector( 2 DOWNTO 0 );
      ...
    );

and I have some individual signals I want to use as the
input to this port, e.g. a2, a1, a0.

I tried:

PORT MAP( ...
          addr => ( a2 & a1 & a0 );
          ...
        );

but the compiler didn't like it.  All I have been able to
come up with is:

PORT MAP( ...
          addr( 2 ) => a2;
          addr( 1 ) => a1;
          addr( 0 ) => a0;
          ...
        );

Surely there's an easier way to do this ...



Tue, 11 Apr 2000 03:00:00 GMT  
 Combining signals as input to a port


SF> Pardon what may be a stupid question, but I'm new to vhdl ...
SF> Suppose I have a port to a component that is an array, e.g.

SF> PORT( ...
SF>       addr : IN std_logic_vector( 2 DOWNTO 0 );
SF>       ...
SF>     );

SF> and I have some individual signals I want to use as the
SF> input to this port, e.g. a2, a1, a0.

SF> I tried:

SF> PORT MAP( ...
SF>           addr => ( a2 & a1 & a0 );
SF>           ...
SF>         );

PORT MAP( ...
          addr => ( a2, a1, a0 );
          ...
        );

should work, or

PORT MAP( ...
          addr => ( 2=>a2, 1=>a1, 0=>a0 );
          ...
        );

chm.
--
Christian Mautner                           Frequentis Vienna, Austria



Fri, 14 Apr 2000 03:00:00 GMT  
 Combining signals as input to a port

Quote:

> Suppose I have a port to a component that is an array, e.g.

> PORT( ...
>       addr : IN std_logic_vector( 2 DOWNTO 0 );
>       ...
>     );

This is called a signal vector, not an array.

Quote:
> I tried:

> PORT MAP( ...
>           addr => ( a2 & a1 & a0 );
>           ...
>         );

> but the compiler didn't like it.  All I have been able to
> come up with is:

I think Cadence's VHDL stuff and Synopsys might like this (from
memory).

Quote:
> Surely there's an easier way to do this ...

It's VHDL... use a temporary signal, assign the signal to the concatuated
signals and assign the signal in the port map.

Loek.

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Sun, 16 Apr 2000 03:00:00 GMT  
 Combining signals as input to a port

Hi folks,

is there a way to use generics in the SGE, e.g. to define a
variable port width? I can't see how the wind blows :-(

So I must edit the generated VHDL(-entity)-code and produce a
mismatch in my sources. This is very ugly for a redesign.

Thanx for your help.

Kind regards,
copi
--
 Heiko Copius
 Technical University of Ilmenau
 Institute of  Microelectronics Systems and Cuircuits
 Dept. of Electrical Engineering and Information Technology
 Postbox 100565
 D-98684 Ilmenau
 Germany

 phone: +49 (0)3677 69 1171
 fax  : +49 (0)3677 69 1163

 www  : http://www.inf-technik.tu-ilmenau.de/~copi



Fri, 21 Apr 2000 03:00:00 GMT  
 Combining signals as input to a port

Quote:

> Hi folks,

> is there a way to use generics in the SGE, e.g. to define a
> variable port width? I can't see how the wind blows :-(

> So I must edit the generated VHDL(-entity)-code and produce a
> mismatch in my sources. This is very ugly for a redesign.

> Thanx for your help.

> Kind regards,
> copi
> --

  (I am doing this from memory, so please refer to your manual for
specifics)

There is no way to define a symbol with variable width ports in
SGE. Being a schematic editor, SGE *has* to know how many pins are
there on the symbol.
However, you can have generics specified on the symbol, which would
appear in the VHDL code generated from that symbol.  I think there are
symbol
attributes (VHDL) called VHDL_Gen1 through VHDL_Gen10 that can be used
to defined arbitrary generic definitions.
Look at the symbol libraries provided with the distribution for
examples. Loading the symbol from $SYNOPSYS/sge/lib/IEEElib/and8.sym
and looking at the symbol attributes (and the generated VHDL entity)
might give you an idea.
Barring this, your only other alternative is to post-process the
generated VHDL with some shell scripts.
Hope that helps.

Sai
--
__________________________________________________________________________

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LogicVision Inc.                   *           (Remove nospam from the
above address)
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Sat, 22 Apr 2000 03:00:00 GMT  
 
 [ 7 post ] 

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