FPGA - Leonardo spectrom+Model tech - timing ??? 
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 FPGA - Leonardo spectrom+Model tech - timing ???

When I finish the synthesis process + P&R I end up with EDIF file that
contains delay information.

How do I apply this delay information onto the VHDL code or is there any
other way to transfer the timing information from the Leonardo back to the
Model tech VHDL simulator in order to simulate my code with the real delay ?

Thanks

Gil



Tue, 29 Jan 2002 03:00:00 GMT  
 FPGA - Leonardo spectrom+Model tech - timing ???
If you'd like to perform a post-synthesis or post-route simulation using
ModelSim VHDL then you'll have to back-annotate a structural VHDL
netlist from your tool(s).  If you'd like to model delay then you should
also back-annotate an SDF (Standard Delay Format)file ...y ou can
specify the region to which to apply the SDF information within
ModelSim. Before you can complile and simulate your back-annotated VHDL
model with delay info from SDF file, you'll need to ensure that your
VITAL (VHDL Initiative Toward ASIC Libraries) library environment is
properly configured and then compile the VITAL compliant libraries for
your target technology (provided by your tool or device supplier).
Quote:

> When I finish the synthesis process + P&R I end up with EDIF file that
> contains delay information.

> How do I apply this delay information onto the VHDL code or is there any
> other way to transfer the timing information from the Leonardo back to the
> Model tech VHDL simulator in order to simulate my code with the real delay ?

> Thanks

> Gil



Wed, 30 Jan 2002 03:00:00 GMT  
 FPGA - Leonardo spectrom+Model tech - timing ???
I'm familiar with the ModelSim, Exemplar, Actel Designer flow (80% of
the FPGA's I design use this flow). I'll be happy to provide you with a
step-by-step procedure, but first I need a couple of details regarding
your tool environment:

a.) Which version of ModelSim are you using (i.e. 5.2e, 4.7i, etc. ...)
? If you're not sure just select Help About ModelSim from within
ModelSim.

b.) Which version of Actel Designer series are you using (i.e. R1-1999,
R3-1998 ...etc.) ? Again, if you're not sure you can select Help About
Designer.

c.) Did you choose to install the Actel VITAL 95 library components when
you installed Actel Designer (I believe that the installation usually
defaults to NOT installing the VITAL libraries). You can check by
browsing the directory into which you installed Designer. On my PC,
Designer is installed in C:\Actel and the source code for the VITAL 95
libraries is found in C:\Actel\lib\vtl\95. You should find several files
with a .VHD extension in this directory. If the VITAL library files are
not installed, you'll need to install them. You can do this by
re-running the Designer installation program ... deselect all
installation components except for Vital Libraries (make sure you
install these Vital libraries into the same location that you originally
installed Designer into).

d.) Which family of Actel device are you using (i.e. 42MX, 3200DX, ACT2
... etc.) ?

e.) Do you plan to use a VHDL test bench to perform you post-route
simulation ?

Quote:

> When I finish the synthesis process + P&R I end up with EDIF file that
> contains delay information.

> How do I apply this delay information onto the VHDL code or is there any
> other way to transfer the timing information from the Leonardo back to the
> Model tech VHDL simulator in order to simulate my code with the real delay ?

> Thanks

> Gil



Wed, 30 Jan 2002 03:00:00 GMT  
 
 [ 3 post ] 

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