Power estimation in VHDL 
Author Message
 Power estimation in VHDL


I am interested in power estimations in VHDL. I also have a
faint memory of reading an article about this topic.

The article described a method to estimate the power consumption
using VHDL. Each unit feedback its load to the driving module via
a resolution function. The driving module then estimates the
power consumption based on the number of "unit loads" attached
to its output.

Does this seem familiar?????

Please send me the reference, or any references to similar

/Peter Sandberg

Peter Sandberg
Division of Applied Electronics                    
ISY, Linkoping University          
581 83  LINKOPING                  

Phone: +46-13284059
Fax:   +46-13139282


Sat, 15 Mar 1997 22:22:32 GMT  
 [ 1 post ] 

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