Simulation flow for top-down design with VHDL 
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 Simulation flow for top-down design with VHDL



Quote:
>The best approach is a VHDL test bench that is used three (or more) times.
>(1)  Verify requirements and design using high level behavi{*filter*}constructs.
>(2)  Verify chip design by testing synthesizable VHDL
>(3)  Verify post synthesis, post place and route, by using VHDL netlist and
>     SDF backannotation.

>Reusing the testbench increases incentive to develop a really good one.
>Using multiple stimulus techniques will tend to make each of them less
>capable than a single one.

>(Most synthesis tools can easily create a VHDL representation of your
>netlist.  Fewer, provide SDF back-annotation, but the list is growing.

>Charles

I must agree with Charles; we had a Zycad, but we found that rerunning the
gate-level sims in VHDL was better.  VHDL sim-times were longer, but the
setup for the Zycad required a large amount of effort:
- converting vectors over to Zycad format
- making sure that you sampled inputs at proper time
- making sure that you strobed outputs at proper time
- making sure either that 1) your unit-delay sim on the Zycad actually
        corresponded in function to the VHDL-RTL sim, or 2) your
        full-annotated sim library on the Zycad corresponded to your
        VHDL-gate level models.

It was much less effort to use VHDL, and you were pretty much able to predict
success (low schedule risk), whereas we were never able to get to that level
of comfort with the Zycad, because it was a different simulator.

The same problem exists in going between any 2 simulators.

We did, however, use the Zycad for fault simulation, where it was extremely
useful.  But, we didn't worry about timing, and we still had to deal with
some messy vector/netlist conversions.

I would recommend buying a faster CPU for your workstation, and leave alone
the Zycad.

(hope nobody from Zycad is reading this)
Erik Jessen



Mon, 09 Mar 1998 03:00:00 GMT  
 Simulation flow for top-down design with VHDL

Quote:
> We did, however, use the Zycad for fault simulation, where it was extremely
> useful.  But, we didn't worry about timing, and we still had to deal with
> some messy vector/netlist conversions.

In a few days I'll be starting an evaluation of something called Attest;
it's an ATG/Partial scan/fault simulator thingy. According to the documentation
I have read so far, on a fast Alpha it's just about as fast as a Zycad.

I'll give a shout when I know more.

Ben.



Sat, 14 Mar 1998 03:00:00 GMT  
 Simulation flow for top-down design with VHDL
: Hello !

: I would like to know which tools do you use for simulation in the case of a
:  top-down approach in VHDL.

We use VOYAGER (from IKOS) as our VHDL simulator.
We have a very high level test harness for the ASIC which incoporates
a 68000 SRAM and DRAM (all from LMC) and a number of other hand-crafted
VHDL models. All aspects of the ASIC can be tested with the one test harness.
Having a 68000 enables us to write C for the various tests.

Having synthisized the gates, we then use the IKOS gate-level simulation
accelerator (NSIM) for simulating the gates. The accelerator gives at least an
order of magnitude greater performance over simulating the ASIC as just RTL VHDL.
We have never bothered simulating the gates using VHDL models of the gates - it's
even slower than simulating the ASIC as RTL VHDL.

Before place and route, we use estimated timing in the gate-level accelerator.
After  place and route, we use the back-annotation file to verify timing.
The gate-level accelerator is timing certified by our ASIC vendor.
We also using static timing analysis just to be on the safe side as well.

The test harness is very comprehensive. It has taken 2-3 man months to develop.
All functional aspects of the ASIC can be tested with the one test harness.
We have a set of test directories. Each directory contains all the files used
by the test harness to enable a specific test to be run. This will be C code
for the 68000 in the test harness, DRAM and SRAM initialization files, and
a number of other src data/ expected data for the other models.

Simulating the design is merely a matter of selecting the appropriate test
directory, and setting off the simulator. In this way, it is very easy
to set off regression tests after any change to the ASIC.

Hope this helps

Andrew Hana
Hewlett Packard (CPB - England).



Sat, 14 Mar 1998 03:00:00 GMT  
 
 [ 3 post ] 

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