don't care in vhdl.. 
Author Message
 don't care in vhdl..

Hi,

I am interested in knowing if there is any way to specify don't-cares in
case statements in VHDL.

e.g. I have the following 2 codes, 1st one in verilog and the 2nd one in
vhdl, which achieve the same thing. But writing the code in vhdl is a pain
for case statements in the following example. This example is still OK,
since I have the sel bit as a 4 input signal. When I go for a 24 bit sel
signal, writing the code in VHDL is getting a nightmare.

The whole objective I want this code to realize is an one-hot  multiplexer...
If I put in a if-elsif statement instead of the case statement, Design Compiler
puts priority encoding logic in the "sel" signal path. I don't want this, since
my "sel" signal is the curr-state of an one-hot statemachine, and I know
that not more than one bit of the sel signal can be a logic '1' at
a time.

Any help on this will be appreciated.

Thanks,
--Rajesh

--------- Verilog Case Statement -------------
casex (sel)
    4'b1xxx: z = d;
    4'bx1xx: z = c;
    4'bxx1x: z = b;
    4'bxxx1: z = a;
    default: z = 1'b0;
endcase
--------------------------------------------

--------- VHDL Case Statement -------------
   process(a,b,c,d,sel)
   begin
       case sel is
           when "1000"|"1001"|"1010"|"1011"|
               "1100"|"1101"|"1110"|"1111" => z <= d;
           when "0100"|"0101"|"0110"|"0111" => z <= c;
           when "0010"|"0011" => z <= b;
           when "0001" => z <= a;
           when others => z <= '0';
       end case;
   end process;
--------------------------------------------
--

Phone : 949-824-1565 (W)
        949-856-2306 (H)
URL   : http://www.*-*-*.com/ ~rajeshs
Office: 120 IERF



Sat, 26 Jan 2002 03:00:00 GMT  
 don't care in vhdl..

Quote:

> Hi,

> I am interested in knowing if there is any way to specify don't-cares in
> case statements in VHDL.

> e.g. I have the following 2 codes, 1st one in verilog and the 2nd one in
> vhdl, which achieve the same thing. But writing the code in vhdl is a pain
> for case statements in the following example. This example is still OK,
> since I have the sel bit as a 4 input signal. When I go for a 24 bit sel
> signal, writing the code in VHDL is getting a nightmare.

> The whole objective I want this code to realize is an one-hot  multiplexer...
> If I put in a if-elsif statement instead of the case statement, Design Compiler
> puts priority encoding logic in the "sel" signal path. I don't want this, since
> my "sel" signal is the curr-state of an one-hot statemachine, and I know
> that not more than one bit of the sel signal can be a logic '1' at
> a time.

> Any help on this will be appreciated.

> Thanks,
> --Rajesh

> --------- Verilog Case Statement -------------
> casex (sel)
>     4'b1xxx: z = d;
>     4'bx1xx: z = c;
>     4'bxx1x: z = b;
>     4'bxxx1: z = a;
>     default: z = 1'b0;
> endcase
> --------------------------------------------

> --------- VHDL Case Statement -------------
>    process(a,b,c,d,sel)
>    begin
>        case sel is
>            when "1000"|"1001"|"1010"|"1011"|
>                "1100"|"1101"|"1110"|"1111" => z <= d;
>            when "0100"|"0101"|"0110"|"0111" => z <= c;
>            when "0010"|"0011" => z <= b;
>            when "0001" => z <= a;
>            when others => z <= '0';
>        end case;
>    end process;
> --------------------------------------------
> --

> Phone : 949-824-1565 (W)
>         949-856-2306 (H)
> URL   : http://www.ics.uci.edu/~rajeshs
> Office: 120 IERF

Try this:

   process(a,b,c,d,sel)
   begin
       case sel is
           when "1000" => z <= d;
           when "0100" => z <= c;
           when "0010" => z <= b;
           when "0001" => z <= a;
           when others => z <= '-';
       end case;
   end process;

It assumes that z is of type STD_ULOGIC. The '-' value of this type
is a "don't care" value. Unfortunately most synthesizers are not
able to exploit this ...

Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13



Sat, 26 Jan 2002 03:00:00 GMT  
 don't care in vhdl..


Quote:

>Hi,

>I am interested in knowing if there is any way to specify don't-cares in
>case statements in VHDL.

>e.g. I have the following 2 codes, 1st one in verilog and the 2nd one in
>vhdl, which achieve the same thing. But writing the code in vhdl is a pain
>for case statements in the following example. This example is still OK,
>since I have the sel bit as a 4 input signal. When I go for a 24 bit sel
>signal, writing the code in VHDL is getting a nightmare.

>The whole objective I want this code to realize is an one-hot  
multiplexer...
>If I put in a if-elsif statement instead of the case statement, Design
Compiler
>puts priority encoding logic in the "sel" signal path. I don't want this,
since
>my "sel" signal is the curr-state of an one-hot statemachine, and I know
>that not more than one bit of the sel signal can be a logic '1' at
>a time.

>Any help on this will be appreciated.

>Thanks,
>--Rajesh

>--------- Verilog Case Statement -------------
>casex (sel)
>    4'b1xxx: z = d;
>    4'bx1xx: z = c;
>    4'bxx1x: z = b;
>    4'bxxx1: z = a;
>    default: z = 1'b0;
>endcase
>--------------------------------------------

>--------- VHDL Case Statement -------------
>   process(a,b,c,d,sel)
>   begin
>       case sel is
>           when "1000"|"1001"|"1010"|"1011"|
>               "1100"|"1101"|"1110"|"1111" => z <= d;
>           when "0100"|"0101"|"0110"|"0111" => z <= c;
>           when "0010"|"0011" => z <= b;
>           when "0001" => z <= a;
>           when others => z <= '0';
>       end case;
>   end process;
>--------------------------------------------
>--

>Phone : 949-824-1565 (W)
>        949-856-2306 (H)
>URL   : http://www.ics.uci.edu/~rajeshs
>Office: 120 IERF

VHDL don't have the don't care the way you know it. You just have to code
it a bit different. In this case I would do like this:

process(a,b,c,d,sel)
begin
        if sel(3) = '1' then            -- Sel(2 donwto 0) are don't care
                z <= d;
        elsif sel(2) = '1' then
                z <= c;
        elsif sel(1) = '1' then
                z <= b;
        elsif sel(0) = '1' then
                z <= a;
        elsif z <= '0';
        end if;
end process

Hi Peter



Sat, 26 Jan 2002 03:00:00 GMT  
 don't care in vhdl..

Quote:

> --------- Verilog Case Statement -------------
> casex (sel)
>     4'b1xxx: z = d;
>     4'bx1xx: z = c;
>     4'bxx1x: z = b;
>     4'bxxx1: z = a;
>     default: z = 1'b0;
> endcase
> --------------------------------------------

I don't actually speak Verilog -- and this just convinces me that
this is a good thing!  I'm very happy that VHDL won't let me do this.
Even more to the point, I'm glad that VHDL won't allow other people,
whose code I may have to modify or maintain, to do this!

Is it clearly defined in Verilog what happens if sel == "1111"???
This matches all four cases, so does z become a, b, c or d?  Will
the result be the same for all synthesis software?  Will it be the
same for all levels and types of optimisation?  Will the result
be the same if you change the order of the four lines in the
case statement?

This is one example where, although you might find VHDL a little less
"convenient" than Verilog, it's clearly giving you at least one fewer
way to shoot yourself in the foot!  You may not find the VHDL alternatives
aesthetically pleasing, but at least they will describe hardware
whose output is clearly defined for all possible inputs.

Incidentally, a more generic approach to your problem might be something
along the following lines.  Instead of having output values a, b, c, and
d you could have a vector of possible output values, one for each state
(this could be a variable whose bits are assigned from a, b, c, and d,
which should not result in any additional hardware being generated).
Assume this vector is called "oput", you can write:

process(oput,sel)
begin
        z <= '0';
        for i in 3 downto 0 loop
                if sel(i) = '1' then
                        z <= oput(i);
                end if;
        end loop;
end process;

It's probably easier to find elegant ways to extend this method to
a large number of bits.  Note that if there is more than one '1' in
sel, the behaviour is clearly defined -- the value of z will be
determined by '1' with the lowest index in sel.  And if sel is all
'0's, then z will be '0'.

Mark



Sat, 26 Jan 2002 03:00:00 GMT  
 don't care in vhdl..
Hi,

you may also take a look at part 1 section 4.2.7 ("Don't Cares" in VHDL)
of the VHDL FAQ at

        http://www.vhdl.org/comp.lang.vhdl/

--
Edwin

Quote:

> Hi,

> I am interested in knowing if there is any way to specify don't-cares in
> case statements in VHDL.

> e.g. I have the following 2 codes, 1st one in verilog and the 2nd one in
> vhdl, which achieve the same thing. But writing the code in vhdl is a pain
> for case statements in the following example. This example is still OK,
> since I have the sel bit as a 4 input signal. When I go for a 24 bit sel
> signal, writing the code in VHDL is getting a nightmare.

> The whole objective I want this code to realize is an one-hot  multiplexer...
> If I put in a if-elsif statement instead of the case statement, Design Compiler
> puts priority encoding logic in the "sel" signal path. I don't want this, since
> my "sel" signal is the curr-state of an one-hot statemachine, and I know
> that not more than one bit of the sel signal can be a logic '1' at
> a time.

> Any help on this will be appreciated.

> Thanks,
> --Rajesh

> --------- Verilog Case Statement -------------
> casex (sel)
>     4'b1xxx: z = d;
>     4'bx1xx: z = c;
>     4'bxx1x: z = b;
>     4'bxxx1: z = a;
>     default: z = 1'b0;
> endcase
> --------------------------------------------

> --------- VHDL Case Statement -------------
>    process(a,b,c,d,sel)
>    begin
>        case sel is
>            when "1000"|"1001"|"1010"|"1011"|
>                "1100"|"1101"|"1110"|"1111" => z <= d;
>            when "0100"|"0101"|"0110"|"0111" => z <= c;
>            when "0010"|"0011" => z <= b;
>            when "0001" => z <= a;
>            when others => z <= '0';
>        end case;
>    end process;
> --------------------------------------------
> --

> Phone : 949-824-1565 (W)
>         949-856-2306 (H)
> URL   : http://www.ics.uci.edu/~rajeshs
> Office: 120 IERF



Sat, 26 Jan 2002 03:00:00 GMT  
 don't care in vhdl..

Quote:


> > --------- Verilog Case Statement -------------
> > casex (sel)
> >     4'b1xxx: z = d;
> >     4'bx1xx: z = c;
> >     4'bxx1x: z = b;
> >     4'bxxx1: z = a;
> >     default: z = 1'b0;
> > endcase
> > --------------------------------------------

> I don't actually speak Verilog -- and this just convinces me that
> this is a good thing!  I'm very happy that VHDL won't let me do this.
> Even more to the point, I'm glad that VHDL won't allow other people,
> whose code I may have to modify or maintain, to do this!

None of your objections is valid, so Verilog still rules.

Quote:

> Is it clearly defined in Verilog what happens if sel == "1111"???

Yes

Quote:

> This matches all four cases, so does z become a, b, c or d?  Will
> the result be the same for all synthesis software?

Yes

Quote:
> Will it be the
> same for all levels and types of optimisation?

Yes

Quote:
> Will the result
> be the same if you change the order of the four lines in the
> case statement?

No, and that is what  I want.

--
Kuba Smieciuszewski       Fujitsu Network Communications, INC



Sat, 26 Jan 2002 03:00:00 GMT  
 don't care in vhdl..

You are right about the priority encoder, so an other way to code
is the following:
- and each signal with its associated select
- or the masked value

You will have to expand the select bits to do that, the simplest
way is probably to code the whole structure; expansion, and,
or into a function.  To make it generic, you may use
- an unconstrained vector of select
- an unconstrained vector of bit = concatenation of all inputs
- an integer defining the size of each input
And return a vector of same size as the input.

Then call it with something like
Output = Mux (Sel, InputN & InputN_1 & ... & Input0, InputSize)

Obviously the results are incorrect if more than one select
is active contrary to the other solutions presented.

Quote:

> Hi,

> I am interested in knowing if there is any way to specify don't-cares in
> case statements in VHDL.

> The whole objective I want this code to realize is an one-hot  multiplexer...
> If I put in a if-elsif statement instead of the case statement, Design Compiler
> puts priority encoding logic in the "sel" signal path. I don't want this, since
> my "sel" signal is the curr-state of an one-hot statemachine, and I know
> that not more than one bit of the sel signal can be a logic '1' at
> a time.

> --------- VHDL Case Statement -------------
>    process(a,b,c,d,sel)
>    begin
>        case sel is
>            when "1000"|"1001"|"1010"|"1011"|
>                "1100"|"1101"|"1110"|"1111" => z <= d;
>            when "0100"|"0101"|"0110"|"0111" => z <= c;
>            when "0010"|"0011" => z <= b;
>            when "0001" => z <= a;
>            when others => z <= '0';
>        end case;
>    end process;
> --------------------------------------------
> --

> Phone : 949-824-1565 (W)
>         949-856-2306 (H)
> URL   : http://www.ics.uci.edu/~rajeshs
> Office: 120 IERF

  vcard.vcf
< 1K Download


Sat, 26 Jan 2002 03:00:00 GMT  
 don't care in vhdl..
Here is one way to get the synthesized design that you want.

Make a function that assumes that the select lines are one-hot.  For example, a
4-to-1 mux could be written as:

function mux4to1 (
    constant select0 : std_logic;  constant data0 : std_logic_vector;
    constant select1 : std_logic;  constant data1 : std_logic_vector;
    constant select2 : std_logic;  constant data2 : std_logic_vector;
    constant select3 : std_logic;  constant data3 : std_logic_vector
    ) return std_logic_vector is

    variable return_value : std_logic_vector (data0'range);
    variable j : integer;

begin
    assert  (data0'high = data1'high) and (data0'low = data1'low)
 and (data1'high = data2'high) and (data1'low = data2'low)
 and (data2'high = data3'high) and (data2'low = data3'low)
 report "mux4to1: data0, data1, data2, and data3 must all have the same highs and
lows"
 severity error;

    for i in data1'range loop
 return_value(i) := (select0 and data0(i))
      or (select1 and data1(i))
      or (select2 and data2(i))
      or (select3 and data3(i));
    end loop;
    return return_value;
end;  -- function mux4to1

process (a,b,c,d,sel)
begin
   z <= mux4to1(sel(0), a, sel(1), b, sel(2), c, sel(3), d);
end process;

Once you have the function, you could even leave out the process and sensitivity
list, and just write a continuous assignment statement, if you wish:

   z <= mux4to1(sel(0), a, sel(1), b, sel(2), c, sel(3), d);

If you want to write a mux with more select lines, I'm a big fan of
Perl/C/whatever-programming-language-you-know for taking parameters (like the 4 in
mux4to1) and automatically generating the proper functions.

Andy

Quote:

> Hi,

> I am interested in knowing if there is any way to specify don't-cares in
> case statements in VHDL.

> e.g. I have the following 2 codes, 1st one in verilog and the 2nd one in
> vhdl, which achieve the same thing. But writing the code in vhdl is a pain
> for case statements in the following example. This example is still OK,
> since I have the sel bit as a 4 input signal. When I go for a 24 bit sel
> signal, writing the code in VHDL is getting a nightmare.

> The whole objective I want this code to realize is an one-hot  multiplexer...
> If I put in a if-elsif statement instead of the case statement, Design Compiler
> puts priority encoding logic in the "sel" signal path. I don't want this, since
> my "sel" signal is the curr-state of an one-hot statemachine, and I know
> that not more than one bit of the sel signal can be a logic '1' at
> a time.

> Any help on this will be appreciated.

> Thanks,
> --Rajesh

> --------- Verilog Case Statement -------------
> casex (sel)
>     4'b1xxx: z = d;
>     4'bx1xx: z = c;
>     4'bxx1x: z = b;
>     4'bxxx1: z = a;
>     default: z = 1'b0;
> endcase
> --------------------------------------------

> --------- VHDL Case Statement -------------
>    process(a,b,c,d,sel)
>    begin
>        case sel is
>            when "1000"|"1001"|"1010"|"1011"|
>                "1100"|"1101"|"1110"|"1111" => z <= d;
>            when "0100"|"0101"|"0110"|"0111" => z <= c;
>            when "0010"|"0011" => z <= b;
>            when "0001" => z <= a;
>            when others => z <= '0';
>        end case;
>    end process;
> --------------------------------------------
> --

> Phone : 949-824-1565 (W)
>         949-856-2306 (H)
> URL   : http://www.ics.uci.edu/~rajeshs
> Office: 120 IERF



Sat, 26 Jan 2002 03:00:00 GMT  
 don't care in vhdl..


|

| >
| > > --------- Verilog Case Statement -------------
| > > casex (sel)
| > >     4'b1xxx: z = d;
| > >     4'bx1xx: z = c;
| > >     4'bxx1x: z = b;
| > >     4'bxxx1: z = a;
| > >     default: z = 1'b0;
| > > endcase
| > > --------------------------------------------
| >
| > I don't actually speak Verilog -- and this just convinces me that
| > this is a good thing!  I'm very happy that VHDL won't let me do this.
| > Even more to the point, I'm glad that VHDL won't allow other people,
| > whose code I may have to modify or maintain, to do this!
|
| None of your objections is valid, so Verilog still rules.
|
| >
| > Is it clearly defined in Verilog what happens if sel == "1111"???
|
| Yes
|
| >
| > This matches all four cases, so does z become a, b, c or d?  Will
| > the result be the same for all synthesis software?
|
| Yes
|
| > Will it be the
| > same for all levels and types of optimisation?
|
| Yes
|
| > Will the result
| > be the same if you change the order of the four lines in the
| > case statement?
| >
|
| No, and that is what  I want.
|

Ouch... I used to think that, if anything VHDL is less readable than
Verilog. If this is an example of what Verilog permits, then maintaining or
reusing a Verilog design must be a complete nightmare!

Just as a matter of interest, what does Verilog assume the designer intended
when more than one condition in a case statement is satisfied?

Regards
Chris Squires
Highwater Designs



Sun, 27 Jan 2002 03:00:00 GMT  
 don't care in vhdl..


Quote:

> Just as a matter of interest, what does Verilog assume the designer intended
> when more than one condition in a case statement is satisfied?

This is a bit late but...

Since Verilog syntax is based on C and since Mr. Smieciuszewski said that
the result of a Verilog case will be different if the order of the
"cases" are changed, I'd think Verilog chooses the first correct
statement (from top to down). It doesn't matter if other statements are
correct when the first one is found. They are not checked.

        - Kalle



Tue, 05 Feb 2002 03:00:00 GMT  
 
 [ 10 post ] 

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