Recursive VHDL models - how to prang your VHDL tools 
Author Message
 Recursive VHDL models - how to prang your VHDL tools

I just worked out how to write recursive models in VHDL to describe
a recursive structures such as trees.  (ok, so you all worked that
out ages ago - I'm a bit slow :-)  

Anyway, I thought I'd code it up and try it out, wondering how the
VHDL tools I'm using would cope with it.  Following is a recursive
model of a fanout tree.  (No documentation - you work it out!)
As I understand VHDL, this model should get recursively generated
during elaboration.

I tried running it using the Synthesia MINT system and the Vantage
Speadsheet system.  MINT compiled everying ok, but crashed with a
Bus Error during elaboration.  Vantage wouldn't even compile it.  It
complained about the recursive binding in the configuration
declaration recursive_fanout_tree, saying that the identifier
recursive_fanout_tree should be a configuration!

If you get a moment to run the code though your favourite VHDL
tools, I'd be pleased to hear how it goes.  Drop me a line to the
e-mail address below, and I'll summarize reports.

Have fun!

PA

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----------------------------------------------------------------
-- tree.vhdl
----------------------------------------------------------------

entity buf is
  port ( a : in bit;
         y : out bit );
end buf;

----------------------------------------------------------------

architecture behaviour of buf is

begin

  y <= a;

end behaviour;

----------------------------------------------------------------

entity fanout_tree is
  generic ( height : positive;
            degree : positive );
  port ( input : in bit;
         output : out bit_vector(0 to degree**height - 1) );
end fanout_tree;

----------------------------------------------------------------

architecture recursive of fanout_tree is

  component buf
    port ( a : in bit;
           y : out bit );
  end component;

  component fanout_tree
    generic ( height : positive;
              degree : positive );
    port ( input : in bit;
           output : out bit_vector(0 to degree**height - 1) );
  end component;

  signal buffered_input : bit_vector(0 to degree - 1);

begin  --  recursive

  simple_tree : if height = 1 generate

    buf_array : for i in 0 to degree - 1 generate

      a_buffer : buf
        port map ( a => input, y => output(i) );

    end generate buf_array;

  end generate simple_tree;

  compound_tree : if height > 1 generate

    subtree_array : for i in 0 to degree - 1 generate

      a_buffer : buf
        port map ( a => input, y => buffered_input(i) );

      a_subtree : fanout_tree
        generic map ( height => height - 1, degree => degree )
        port map ( input => buffered_input(i),
                   output => output(i * degree**(height-1)
                                    to (i+1) * degree**(height-1) -1) );

    end generate subtree_array;

  end generate compound_tree;

end recursive;

----------------------------------------------------------------

configuration recursive_fanout_tree of fanout_tree is

  for recursive

    for simple_tree
      for buf_array
        for a_buffer : buf
          use entity work.buf(behaviour);
        end for;
      end for;
    end for;

    for compound_tree
      for subtree_array
        for a_buffer : buf
          use entity work.buf(behaviour);
        end for;
        for a_subtree : fanout_tree
          use configuration recursive_fanout_tree;
        end for;
      end for;
    end for;

  end for;

end recursive_fanout_tree;

----------------------------------------------------------------

entity tree_test is

end tree_test;

----------------------------------------------------------------

architecture bench of tree_test is

  constant test_height : positive := 3;
  constant test_degree : positive := 2;

  signal clock : bit;
  signal buffered_clock : bit_vector(0 to test_degree**test_height - 1);

  component fanout_tree
    generic ( height : positive;
              degree : positive );
    port ( input : in bit;
           output : out bit_vector(0 to degree**height - 1) );
  end component;

begin  --  bench

  dut : fanout_tree
    generic map ( height => test_height, degree => test_degree )
    port map ( input => clock, output => buffered_clock );

  clock_gen : process
  begin
    clock <= '1' after 1 ns, '0' after 2 ns;
    wait for 2 ns;
  end process clock_gen;

end bench;

----------------------------------------------------------------

configuration test_fanout_tree of tree_test is

  for bench

    for dut : fanout_tree
      use configuration recursive_fanout_tree;
    end for;

  end for;

end test_fanout_tree;



Tue, 23 Apr 1996 00:21:00 GMT  
 
 [ 1 post ] 

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