"configure top-level entity"?? 
Author Message
 "configure top-level entity"??

Hi all, a small question regarding an error message I am getting.
I am working on a test bench for a vhdl file I have made. I am using
synopsys as the tool to simulate this test bench to see if my vhdl file
is correct or not.
Now, my vhdl file and the test bench are compiling fine (using vhdlan
-nc), but when I try to simulate the test bench, I get the message: "Top
level entity/architecture must be configured before it can be
simulated".
Any ideas on what I am doing wrong, or what I am missing?
Thanks a lot in advance.
Sincerely,

KZA



Mon, 05 Aug 2002 03:00:00 GMT  
 "configure top-level entity"??
Hi,
   In principle the simulator should be able to do a "default binding" - but
this gets complicated (I never do this, so I don't know) when the design
(your vhdl file) is compiled into a different library and testbench into
another. The easiest would be do write a small "configuration" file. Consult
any good book on VHDL else the FAQ at
http://www.vhdl.org/comp.lang.vhdl

It would be easier if you can just post a skeleton of your code.

Srini
--
Srinivasan V
IC Design Engineer,
Philips Semiconductors, Eindhoven,
The Netherlands


Quote:
> Hi all, a small question regarding an error message I am getting.
> I am working on a test bench for a vhdl file I have made. I am using
> synopsys as the tool to simulate this test bench to see if my vhdl file
> is correct or not.
> Now, my vhdl file and the test bench are compiling fine (using vhdlan
> -nc), but when I try to simulate the test bench, I get the message: "Top
> level entity/architecture must be configured before it can be
> simulated".
> Any ideas on what I am doing wrong, or what I am missing?
> Thanks a lot in advance.
> Sincerely,

> KZA



Mon, 05 Aug 2002 03:00:00 GMT  
 "configure top-level entity"??
On Thu, 17 Feb 2000 06:08:37 GMT, Khurram Z. Agha


Quote:
> Hi all, a small question regarding an error message I am getting.
> I am working on a test bench for a vhdl file I have made. I am using
> synopsys as the tool to simulate this test bench to see if my vhdl file
> is correct or not.
> Now, my vhdl file and the test bench are compiling fine (using vhdlan
> -nc), but when I try to simulate the test bench, I get the message: "Top
> level entity/architecture must be configured before it can be
> simulated".
> Any ideas on what I am doing wrong, or what I am missing?

IIRC, VSS requires a top-level configuration to activate default
binding.  IOW, one cannot specify a entity-architecture pair at the
top level--it must be a configuration, even one as simple as:

        configuration Top of TopLevelEntity is
          for TopLevelArchitecture
          end for;
        end;

Paul

--
Paul Menchini   |  "Outside of a dog, a book is probably man's
Cadence PDS     |   best friend, and inside of a dog, it's too

www.orcad.com   |       --Groucho Marx



Mon, 05 Aug 2002 03:00:00 GMT  
 
 [ 3 post ] 

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