RTL & process 
Author Message
 RTL & process

Can we use process in RTL design without ANY problem when synthesize
come or can we only use concurrent assignement?

Sent via Deja.com http://www.*-*-*.com/
Before you buy.



Tue, 28 Jan 2003 03:00:00 GMT  
 RTL & process
Hi,
  Yes VERY MUCH! I wonder why you ask this - did you have any problem with
Processes usage? If so do post the same.

Srini

Quote:
> Can we use process in RTL design without ANY problem when synthesize
> come or can we only use concurrent assignement?

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Tue, 28 Jan 2003 03:00:00 GMT  
 RTL & process
No, I don't have problem with process. It's just that now I'm a little
bit confuse with what is or cannot be synthesize. I think I'm gonna buy
a book that deal with that! Any recommandation?

Quote:
> Hi,
>   Yes VERY MUCH! I wonder why you ask this - did you have any problem
with
> Processes usage? If so do post the same.

> Srini


> > Can we use process in RTL design without ANY problem when synthesize
> > come or can we only use concurrent assignement?

> > Sent via Deja.com http://www.deja.com/
> > Before you buy.

Sent via Deja.com http://www.deja.com/
Before you buy.


Wed, 29 Jan 2003 03:00:00 GMT  
 RTL & process
Hi lois,
read this :

IEEE P1076.6/D1.12
Draft Standard For VHDL Register
Transfer Level Synthesis

Have a nice synthesis

  Eilert

Quote:
>>>>>>>>>>>>>>>>>> Ursprngliche Nachricht <<<<<<<<<<<<<<<<<<


Re: RTL & process:
Quote:
> No, I don't have problem with process. It's just that now I'm a little
> bit confuse with what is or cannot be synthesize. I think I'm gonna buy
> a book that deal with that! Any recommandation?
> > Hi,
> >   Yes VERY MUCH! I wonder why you ask this - did you have any problem
> with
> > Processes usage? If so do post the same.

> > Srini


> > > Can we use process in RTL design without ANY problem when synthesize
> > > come or can we only use concurrent assignement?

> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.

> Sent via Deja.com http://www.deja.com/
> Before you buy.



Fri, 31 Jan 2003 03:00:00 GMT  
 RTL & process
Where I'm suppose to get this?

Quote:
> IEEE P1076.6/D1.12
> Draft Standard For VHDL Register
> Transfer Level Synthesis

> Have a nice synthesis

>   Eilert

> >>>>>>>>>>>>>>>>>> Urspr=FCngliche Nachricht <<<<<<<<<<<<<<<<<<


Thema=
> =20
> Re: RTL & process:

> > No, I don't have problem with process. It's just that now I'm a
little=

> > bit confuse with what is or cannot be synthesize. I think I'm gonna
bu=
> y
> > a book that deal with that! Any recommandation?

> > > Hi,
> > >   Yes VERY MUCH! I wonder why you ask this - did you have any
proble=
> m
> > with
> > > Processes usage? If so do post the same.

> > > Srini


> > > > Can we use process in RTL design without ANY problem when
synthesi=
> ze
> > > > come or can we only use concurrent assignement?

> > > > Sent via Deja.com http://www.deja.com/
> > > > Before you buy.

> > Sent via Deja.com http://www.deja.com/
> > Before you buy.

Sent via Deja.com http://www.deja.com/
Before you buy.


Fri, 31 Jan 2003 03:00:00 GMT  
 RTL & process


Quote:
>Where I'm suppose to get this?

>> IEEE P1076.6/D1.12
>> Draft Standard For VHDL Register
>> Transfer Level Synthesis

You have to buy it from the IEEE. If you've already got it, section
6(?) gives a useful set of templates. The document is a work in
progress, and has been shaped by legal issues as much as anything
else, and I wouldn't recommend buying it.

I don't know of a good book that deals solely with synthesis, and
you'd probably get far too much detail if you did buy one. David
Bishop wrote a synthesis chapter in Peter Ashenden's book that would
be a good starting point.

Actel used to publish a small white book, called 'HDL style guide', or
something similar, which would also be a good starting point. You may
be able to get one from an Actel rep.

Evan



Sat, 01 Feb 2003 03:00:00 GMT  
 RTL & process

The Actel book is available as a PDF - from
http://www.actel.com/docs/29105_0.pdf

 - Bren


Quote:


> >Where I'm suppose to get this?

> >> IEEE P1076.6/D1.12
> >> Draft Standard For VHDL Register
> >> Transfer Level Synthesis

> You have to buy it from the IEEE. If you've already got it, section
> 6(?) gives a useful set of templates. The document is a work in
> progress, and has been shaped by legal issues as much as anything
> else, and I wouldn't recommend buying it.

> I don't know of a good book that deals solely with synthesis, and
> you'd probably get far too much detail if you did buy one. David
> Bishop wrote a synthesis chapter in Peter Ashenden's book that would
> be a good starting point.

> Actel used to publish a small white book, called 'HDL style guide', or
> something similar, which would also be a good starting point. You may
> be able to get one from an Actel rep.

> Evan



Sat, 01 Feb 2003 03:00:00 GMT  
 RTL & process

Quote:



> >Where I'm suppose to get this?

> >> IEEE P1076.6/D1.12
> >> Draft Standard For VHDL Register
> >> Transfer Level Synthesis

> You have to buy it from the IEEE. If you've already got it, section
> 6(?) gives a useful set of templates. The document is a work in
> progress, and has been shaped by legal issues as much as anything
> else, and I wouldn't recommend buying it.

> I don't know of a good book that deals solely with synthesis, and
> you'd probably get far too much detail if you did buy one. David
> Bishop wrote a synthesis chapter in Peter Ashenden's book that would
> be a good starting point.

> Actel used to publish a small white book, called 'HDL style guide', or
> something similar, which would also be a good starting point. You may
> be able to get one from an Actel rep.

> Evan

Please let me clarify.  If you are looking for an old draft of the
standard, you
can get it from the web site http://www.vhdl.org/siwg.  However 1076.6 is

officially an IEEE standard. So if you want the IEEE standard version of
the
document, you will have to purchase it from IEEE.

Quote:
>> The document is a work in
>> progress, and has been shaped by legal issues as much as anything

The IEEE standard document is NOT a work in progress. It describes the
IEEE VHDL RTL Synthesizable subset standard.

There have been no legal issues that have impacted the development of the
standard.

- bhasker
   Chair, IEEE Working Group 1076.6



Tue, 04 Feb 2003 03:00:00 GMT  
 RTL & process
On Fri, 18 Aug 2000 16:33:24 -0400, "J. Bhasker"

Quote:


>>> The document is a work in
>>> progress, and has been shaped by legal issues as much as anything

>The IEEE standard document is NOT a work in progress. It describes the
>IEEE VHDL RTL Synthesizable subset standard.

>There have been no legal issues that have impacted the development of the
>standard.

>- bhasker
>   Chair, IEEE Working Group 1076.6

I stand by my statement that it is a work in progress. The Level 1
standard, which is now 1076.6, is simply a stopgap on the way to the
Level 2 standard. The primary reasons for this were a legal issue
relating to Synopsys patents, and the desire to include only the
then-current state of DC in 1997.

In addition, the Level 1 standard is essentially unimplementable, and
could only be justified on the grounds that it was a basis for the
Level 2 standard. The reasons for this are detailed, and I don't
propose to bring them up here again. However, anyone who's interested
can find a summary of some of the issues in the WG mailing list
(http://www.eda.org/siwg) in threads starting in September last year.

Evan

__________________________
E.M. Lavelle
Riverside Machines Ltd.

__________________________



Wed, 05 Feb 2003 03:00:00 GMT  
 
 [ 9 post ] 

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