a simple question 
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 a simple question


> Dear all:  i have used Verilog for a long time ,and just learn to use
> VHDL ,i'm very confused about the TYPE of VHDL,seems VHDL check the TYPE
> of operand very strict and this make me very inconvenient,example:  in
> Verilog  reg [7:0]  a,b,c;  always (posedge clk)  c <=a+b;  if (c[7])
> ............  in VHDL:  if i want to use operator "+" , i have to define a
> ,b, c as INTEGER,but if i wnat to access individual bit of a,b,c , i have
> to define a,b,c as BIT_VECTOR,,it make me very tired,i'm not sure whether
> this is the truth of VHDL,can anybody give me a explain and a good method
> to resolve this?  thanks advanced!

You could use a dedicated package allowing to do mathematics with
bitvector style values. For instance, Synopsys provides a package
STD_LOGIC_ARITH with types UNSIGNED and SIGNED. Operations such as
"+", "-", "*" are defined for these types, and bit-wise access to
them is possible as well. There are also conversion functions to
convert values of these types to and from INTEGER, BIT_VECTOR, and
STD_LOGIC types. All this is synthesizable with Synopsys. Other
vendors should have similar packages.

There also exists an IEEE standard NUMERIC_STD package providing the
same functionality in a standardized way. I don't know whether this is
supported by the vendors; anyway, it should be possible to compile it
for simulation (synthesis might fail).

 Martin Radetzki                                Tel.: **49-441-798-2988
 OFFIS Research Institute                       Fax.: **49-441-798-2145
 Escherweg 2             http://www.*-*-*.com/ ~martin

Mon, 22 May 2000 03:00:00 GMT  
 [ 2 post ] 

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