VHDL/Verilog -- Co-simulate or convert 
Author Message
 VHDL/Verilog -- Co-simulate or convert

If given the task of coordinating a co-development with
two other sites, one designing with Verilog and the other
with VHDL, what would be the optimal design verification
solution available today?   Does anyone have experiences
relative to:

o Co-simulation

   What co-simulation solutions exist today?
   Are these backplane solutions robust enough?  Performance?

o Converting the Verilog design to VHDL or vice versa

   What tools are available?  Accuracy of conversion?  Time
   to convert?  

o Single engine simulators.

   Redwood ..... others?

Thanks,

Ernie

--
----------------------------------------------------------------------

Platform Hardware & Architecture    
AT&T Global Information Solutions      Columbia, South Carolina



Sun, 24 Nov 1996 23:54:18 GMT  
 VHDL/Verilog -- Co-simulate or convert

Quote:

>If given the task of coordinating a co-development with
>two other sites, one designing with Verilog and the other
>with VHDL, what would be the optimal design verification
>solution available today?   Does anyone have experiences
>relative to:

...
>o Converting the Verilog design to VHDL or vice versa

>   What tools are available?  Accuracy of conversion?  Time
>   to convert?  


about 95% of the language.  Convesion time negligible.

Eli
--
Eli Sterheim
interHDL inc.
1270 Oakmead PkWy, #207
Sunnyvale, CA 94086
Tel (408) 749-8775
FAX (408) 749-8823



Tue, 26 Nov 1996 07:46:01 GMT  
 VHDL/Verilog -- Co-simulate or convert

Quote:

>If given the task of coordinating a co-development with
>two other sites, one designing with Verilog and the other
>with VHDL, what would be the optimal design verification
>solution available today?   Does anyone have experiences
>relative to:
>o Co-simulation
>   What co-simulation solutions exist today?
>   Are these backplane solutions robust enough?  Performance?
>o Converting the Verilog design to VHDL or vice versa
>   What tools are available?  Accuracy of conversion?  Time
>   to convert?  
>o Single engine simulators.
>   Redwood ..... others?
>Thanks,
>Ernie
>--
>----------------------------------------------------------------------

>Platform Hardware & Architecture    
>AT&T Global Information Solutions      Columbia, South Carolina

Cadence have a co-simulator (Cadence Leapfrog)

I haven't used it, but it looks good, and they will be improving the
functionality.

What other co-simulators are there around ?

--
-------------------------------------------------------------------
John Webster                                     ARM Ltd.
              Phone  0223 400468                 Fulbourn Road

                                                 Cambridge  CB1 4JN
-------------------------------------------------------------------



Mon, 25 Nov 1996 23:08:21 GMT  
 VHDL/Verilog -- Co-simulate or convert


Quote:

> If given the task of coordinating a co-development with
> two other sites, one designing with Verilog and the other
> with VHDL, what would be the optimal design verification
> solution available today?   Does anyone have experiences
> relative to:

> o Co-simulation

>    What co-simulation solutions exist today?
>    Are these backplane solutions robust enough?  Performance?

I just received product literature from Cadence.  They apparently provide
something called "model import".  This combines a Verilog-XL Turbo
license with a Leapfrog VHDL "slave" license to co-simulate the HDL
engines in a single design.

If you are using the Verilog user interface, the complete simulation
looks to the user exactly like a Verilog-XL run.

Good luck

Dave
--

  Delco Electronics Corp.        Phone: 317-451-0874
  Kokomo, Indiana  46904-9005    
===========================================================================



Tue, 26 Nov 1996 20:54:34 GMT  
 VHDL/Verilog -- Co-simulate or convert

Quote:
> Cadence have a co-simulator (Cadence Leapfrog)

To be more specific, Cadence Leapfrog is a VHDL simulator.  It can
cosimulate with Verilog-XL from Cadence.  In a non-backplane version,
we call it Verilog model import into Leapfrog.  There is a similar
capability to import VHDL models from Leapfrog into Verilog-XL.

/Steve
--
------------------------------------------------------------------------------
Steve Greenberg                         Phone: (508) 446-6231
Cadence Design Systems, Inc.            FAX:   (508) 446-6636

Chelmsford, MA 01824
Disclaimer: The standard disclaimer applies



Sat, 30 Nov 1996 02:22:50 GMT  
 VHDL/Verilog -- Co-simulate or convert

Quote:
>I just received product literature from Cadence.  They apparently provide
>something called "model import".  This combines a Verilog-XL Turbo
>license with a Leapfrog VHDL "slave" license to co-simulate the HDL
>engines in a single design.

I'm currently using a VHDL Leapfrog license with a "slave" Verilog-XL
license to link in the Logic Modelling hardware modeller to a VHDL system
simulation.

Cadence supply software utilities which create a Verilog interface module
from the Logic Modelling shell software, and in turn create a VHDL entity
from the Verilog module.

On simulation the VHDL entity calls up the Verilog module (and the slave
Verilog-XL license) and the verilog module calls up the LM hardware modeller.
To the user, it looks like a normal VHDL simulation, and because the utilities
create all the necessary Verilog and VHDl interface models automatically, once
you've created the shell software for the actual hardware to be simulated, its
remarkably easy to use.

Course if Cadence had created a proper C interface to Leapfrog I wouldn't have to
use Verilog at all!!

BaRD.
--------------------------------------------------------------------
You can measure a programmer's perspective by noting his attitude on
the continuing viability of fortran.
                -- Alan Perlis



Fri, 29 Nov 1996 17:34:59 GMT  
 
 [ 6 post ] 

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