Don't Care in a with...select? 
Author Message
 Don't Care in a with...select?

VHDL newbie question.  I've got a working design, with one awkward
thing.

        with cpu_addr select
                register_decode <= camera when "00000",
                        camera when "00001",
                        camera when "00010",
                        camera when "00011",
                        camera when "00100",
                        camera when "00101",
                        camera when "00110",
                        camera when "00111",
                        camera when "01000",
                        camera when "01001",
                        camera when "01010",
                        camera when "01011",
                        camera when "01100",
                        camera when "01101",
                        camera when "01110",
                        camera when "01111",
                        status when "10000",
                        sram when "10001",
                        countl when "10010",
                        counth when "10011",
                        counthb when "10100",
                        noport when others;

This would be concisely expressed by:

        with cpu_addr select
                register_decode <= camera when "0----",
                        status when "10000",
                        sram when "10001",
                        countl when "10010",
                        counth when "10011",
                        counthb when "10100",
                        noport when others;

but the compiler objects.  Can it be accomplished by using the right
library?  Or is there a better construct?

--

Intelligent Sensors
Sandia National Laboratories
Albuquerque, New Mexico, USA



Tue, 13 Jul 2004 00:46:51 GMT  
 Don't Care in a with...select?

Quote:

> VHDL newbie question.  I've got a working design, with one awkward
> thing.

> This would be concisely expressed by:

>         with cpu_addr select
>                 register_decode <= camera when "0----",
>                         status when "10000",
>                         sram when "10001",
>                         countl when "10010",
>                         counth when "10011",
>                         counthb when "10100",
>                         noport when others;

> but the compiler objects.  Can it be accomplished by using the right
> library?  Or is there a better construct?

process (cpu_addr)
begin
        if cpu_addr(4) = '0' then
                register_decode <= camera ;
        else
                case cpu_addr(3 downto 0) is
                        when "0000" => register_decode <= status;
                  etc.
                end case;
        end if;
end process;

is one solution

--

  L_   _|   Senior Design Engineer
    | |     Tality, Alba Campus, Livingston EH54 7HH, Scotland
    ! |     Phone: +44 1506 595360        Fax: +44 1506 595959

T A L I T Y                http://www.tality.com



Tue, 13 Jul 2004 02:05:44 GMT  
 Don't Care in a with...select?
Hi,

Quote:

> VHDL newbie question.  I've got a working design, with one awkward
> thing.

>    with cpu_addr select
>            register_decode <= camera when "00000",
>                    camera when "00001",
>                    camera when "00010",
>                    camera when "00011",
>                    camera when "00100",
>                    camera when "00101",
>                    camera when "00110",
>                    camera when "00111",
>                    camera when "01000",
>                    camera when "01001",
>                    camera when "01010",
>                    camera when "01011",
>                    camera when "01100",
>                    camera when "01101",
>                    camera when "01110",
>                    camera when "01111",
>                    status when "10000",
>                    sram when "10001",
>                    countl when "10010",
>                    counth when "10011",
>                    counthb when "10100",
>                    noport when others;

> This would be concisely expressed by:

>    with cpu_addr select
>            register_decode <= camera when "0----",
>                    status when "10000",
>                    sram when "10001",
>                    countl when "10010",
>                    counth when "10011",
>                    counthb when "10100",
>                    noport when others;

Try

register_decode <= camera when cpu_addr(4) = '0' else
                   status when cpu_addr = "10000" else

           sram when cpu_atr = "10001" else ...      

You may also take a look at the VHDL FAQ:

        http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#dont_cares

--
Edwin



Tue, 13 Jul 2004 03:53:16 GMT  
 Don't Care in a with...select?


Quote:
> VHDL newbie question.  I've got a working design, with one awkward
> thing.

>    with cpu_addr select
>            register_decode <= camera when "00000",
>                    camera when "00001",
>                    camera when "00010",
>                    camera when "00011",
>                    camera when "00100",
>                    camera when "00101",
>                    camera when "00110",
>                    camera when "00111",
>                    camera when "01000",
>                    camera when "01001",
>                    camera when "01010",
>                    camera when "01011",
>                    camera when "01100",
>                    camera when "01101",
>                    camera when "01110",
>                    camera when "01111",
>                    status when "10000",
>                    sram when "10001",
>                    countl when "10010",
>                    counth when "10011",
>                    counthb when "10100",
>                    noport when others;

> This would be concisely expressed by:

>    with cpu_addr select
>            register_decode <= camera when "0----",
>                    status when "10000",
>                    sram when "10001",
>                    countl when "10010",
>                    counth when "10011",
>                    counthb when "10100",
>                    noport when others;

> but the compiler objects.  Can it be accomplished by using the right
> library?  Or is there a better construct?

Your target logic doesn't have a '-' state so the synthesizer can't
build the "0----" AND gate.  Remember, '-' is a logic state, not a
don't care to be synthesized away.  

This would work in a testbench, but  the simulator would be looking for
a "0----" on the inputs to make the output true. A "00000" wouldn't
pass, because '-' <> '0'.

-----
  Keith



Tue, 13 Jul 2004 05:19:55 GMT  
 Don't Care in a with...select?
If you use ieee.numeric_std (recommended), thenyou can use the match
function in that package to do this.

Quote:



> > VHDL newbie question.  I've got a working design, with one awkward
> > thing.

> >       with cpu_addr select
> >               register_decode <= camera when "00000",
> >                       camera when "00001",
> >                       camera when "00010",
> >                       camera when "00011",
> >                       camera when "00100",
> >                       camera when "00101",
> >                       camera when "00110",
> >                       camera when "00111",
> >                       camera when "01000",
> >                       camera when "01001",
> >                       camera when "01010",
> >                       camera when "01011",
> >                       camera when "01100",
> >                       camera when "01101",
> >                       camera when "01110",
> >                       camera when "01111",
> >                       status when "10000",
> >                       sram when "10001",
> >                       countl when "10010",
> >                       counth when "10011",
> >                       counthb when "10100",
> >                       noport when others;

> > This would be concisely expressed by:

> >       with cpu_addr select
> >               register_decode <= camera when "0----",
> >                       status when "10000",
> >                       sram when "10001",
> >                       countl when "10010",
> >                       counth when "10011",
> >                       counthb when "10100",
> >                       noport when others;

> > but the compiler objects.  Can it be accomplished by using the right
> > library?  Or is there a better construct?

> Your target logic doesn't have a '-' state so the synthesizer can't
> build the "0----" AND gate.  Remember, '-' is a logic state, not a
> don't care to be synthesized away.

> This would work in a testbench, but  the simulator would be looking for
> a "0----" on the inputs to make the output true. A "00000" wouldn't
> pass, because '-' <> '0'.

> -----
>   Keith

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Tue, 13 Jul 2004 06:58:24 GMT  
 Don't Care in a with...select?
I keep finding out about new (to me) functions in some of the various
libraries.  Is there a good reference (preferably on line in in the ise
documentation) that lists all these wonderful functions.  (I just recently
found out about the rising_edge and falling_edge functions instead of the
slightly less obvious

clock'event and clock='1'

).
Thanks,
Theron Hicks

Quote:

> If you use ieee.numeric_std (recommended), thenyou can use the match
> function in that package to do this.




> > > VHDL newbie question.  I've got a working design, with one awkward
> > > thing.

> > >       with cpu_addr select
> > >               register_decode <= camera when "00000",
> > >                       camera when "00001",
> > >                       camera when "00010",
> > >                       camera when "00011",
> > >                       camera when "00100",
> > >                       camera when "00101",
> > >                       camera when "00110",
> > >                       camera when "00111",
> > >                       camera when "01000",
> > >                       camera when "01001",
> > >                       camera when "01010",
> > >                       camera when "01011",
> > >                       camera when "01100",
> > >                       camera when "01101",
> > >                       camera when "01110",
> > >                       camera when "01111",
> > >                       status when "10000",
> > >                       sram when "10001",
> > >                       countl when "10010",
> > >                       counth when "10011",
> > >                       counthb when "10100",
> > >                       noport when others;

> > > This would be concisely expressed by:

> > >       with cpu_addr select
> > >               register_decode <= camera when "0----",
> > >                       status when "10000",
> > >                       sram when "10001",
> > >                       countl when "10010",
> > >                       counth when "10011",
> > >                       counthb when "10100",
> > >                       noport when others;

> > > but the compiler objects.  Can it be accomplished by using the right
> > > library?  Or is there a better construct?

> > Your target logic doesn't have a '-' state so the synthesizer can't
> > build the "0----" AND gate.  Remember, '-' is a logic state, not a
> > don't care to be synthesized away.

> > This would work in a testbench, but  the simulator would be looking for
> > a "0----" on the inputs to make the output true. A "00000" wouldn't
> > pass, because '-' <> '0'.

> > -----
> >   Keith

> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950

> http://www.andraka.com

>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759



Tue, 13 Jul 2004 10:31:50 GMT  
 Don't Care in a with...select?
Hi,
  Check out Section 4.8.1 of FAQ Part 1
http://www.eda.org/comp.lang.vhdl/FAQ1.html
4.8.1 Functions and Operators Defined in Package numeric_std



Quote:
> I keep finding out about new (to me) functions in some of the
various
> libraries.  Is there a good reference (preferably on line in in the
ise
> documentation) that lists all these wonderful functions.  (I just
recently
> found out about the rising_edge and falling_edge functions instead
of the
> slightly less obvious

> clock'event and clock='1'

> ).
> Thanks,
> Theron Hicks

<SNIP>

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"I don't Speak for Intel"



Tue, 13 Jul 2004 13:26:58 GMT  
 Don't Care in a with...select?
Thanks for all the suggestions, folks.  I went through this whole
exercise just because I could make a process look prettier with a
case...is than an if...then...else.  Like I said, I have a working
design, and I was just playing around trying to get a better feel for
VHDL.  I finally used:

        register_decode <=
                camera  when cpu_addr < "10000" else
                status  when cpu_addr = "10000" else
                sram    when cpu_addr = "10001" else
                countl  when cpu_addr = "10010" else
                counth  when cpu_addr = "10011" else
                counthb when cpu_addr = "10100" else
                noport;

I'm gradually getting a handle on the conflict between simulation and
synthesis.



Quote:
> Your target logic doesn't have a '-' state so the synthesizer can't
> build the "0----" AND gate.  Remember, '-' is a logic state, not a
> don't care to be synthesized away.  

> This would work in a testbench, but  the simulator would be looking for
> a "0----" on the inputs to make the output true. A "00000" wouldn't

--

Intelligent Sensor Systems
Sandia National Laboratories
Albuquerque, New Mexico, USA


Wed, 14 Jul 2004 00:26:48 GMT  
 Don't Care in a with...select?


Quote:
> Thanks for all the suggestions, folks.  I went through this whole
> exercise just because I could make a process look prettier with a
> case...is than an if...then...else.  Like I said, I have a working
> design, and I was just playing around trying to get a better feel for
> VHDL.  I finally used:

>    register_decode <=
>            camera  when cpu_addr < "10000" else

Oohhh! That looks dangerous to me.  I'd rather the synthesis tools not
have to know about anything other than equality unless absolutely
necessary (you really do have inequalities).  Remember, the synthesis
tool is going to compare your code against templates in order to
generate gates.  That '<' would indicate to me an adder(subtract). Your
synthesis tool might get this right this time (did you look at the
logic generated?), but down the road you may get an adder where you
didn't want one. A bunch of equalities is simply a bunch of and gates.  

Another reason I wouldn't go this way would be simply for clarity.  
Next year when the thing breaks, I'd rather not have to figure out why
I was doing a magnitude comparison.  The statements enumerating the
possible cases is much clearer.  The original might be a little verbose
(VHDL is like that ;-) but the unnecessary logic is going to be
squished out by the synthesizer anyway.

I'd likely go with one of the if-then-elsif constructs others have
mentioned or leave it as it was. It was very clear, if a little
verbose.  I always vote for clear. I know I'll have to live with it!

Quote:
>            status  when cpu_addr = "10000" else
>            sram    when cpu_addr = "10001" else
>            countl  when cpu_addr = "10010" else
>            counth  when cpu_addr = "10011" else
>            counthb when cpu_addr = "10100" else
>            noport;

> I'm gradually getting a handle on the conflict between simulation and
> synthesis.

Yes, you'll have that!  It wasn't long ago that I was *totally*
stumped.  I've graduated to mostly confused. ;-)

----
  Keith



Wed, 14 Jul 2004 03:28:50 GMT  
 Don't Care in a with...select?


Quote:
> >       register_decode <=
> >               camera  when cpu_addr < "10000" else

> Oohhh! That looks dangerous to me. ...

Well, I could have written "when cpu_addr(4) = '0'" but the logic is the
same.  I'm fitting this to a Cypress CY37128 PLD, so the issues aren't
quite the same as if I were doing it for an FPGA, which I think is your
concern.

All this aggravation just to implement a frame buffer for a CMOS B&W
video camera chip :).  I've done programmable logic from time to time
for the last 15 years.  This time I discovered that VHDL seemed to have
pretty much taken over while I was away.

This is the fanciest part (and first by Cypress) that I've used.  I've
got a full-frame (385x288) and a 1/4-frame (every other pixel and line)
capture mode.  Just the PLD and a 128K x 8 SRAM interfaced to a 386EX
SBC.  Fun little project.

--

Intelligent Sensors
Sandia National Laboratories
Albuquerque, New Mexico, USA



Wed, 14 Jul 2004 04:31:19 GMT  
 Don't Care in a with...select?


Quote:


> > >  register_decode <=
> > >          camera  when cpu_addr < "10000" else

> > Oohhh! That looks dangerous to me. ...

> Well, I could have written "when cpu_addr(4) = '0'" but the logic is the
> same.

Actually, you can't (at least I don't think so).  That would take an
if-then-else sort of thing.  I believe all the "when"s have to be on
the same variable/range.

Quote:
> I'm fitting this to a Cypress CY37128 PLD, so the issues aren't
> quite the same as if I were doing it for an FPGA, which I think is your
> concern.

Understoood. It is different, I guess. I'd still be leery of telling
the synth that I wanted to do arithmetic.

Quote:
> All this aggravation just to implement a frame buffer for a CMOS B&W
> video camera chip :).  I've done programmable logic from time to time
> for the last 15 years.  This time I discovered that VHDL seemed to have
> pretty much taken over while I was away.

:-)  I only switched from schematic to VHDL three years ago.  I'm not
convinced it was absolutely the right way to go then (for FPGA design),
but it worked out since I'm now doing processor verification and the
design is in "VHDL".

Quote:
> This is the fanciest part (and first by Cypress) that I've used.  I've
> got a full-frame (385x288) and a 1/4-frame (every other pixel and line)
> capture mode.  Just the PLD and a 128K x 8 SRAM interfaced to a 386EX
> SBC.  Fun little project.

So I can see from your signature. Just don't point your camera this
way.  I get nervous looking up barrels. ;-)

----
   Keith



Wed, 14 Jul 2004 05:00:54 GMT  
 Don't Care in a with...select?


Quote:
> > Well, I could have written "when cpu_addr(4) = '0'" but the logic is the
> > same.

> Actually, you can't (at least I don't think so).  That would take an
> if-then-else sort of thing.  I believe all the "when"s have to be on
> the same variable/range.

Actually, it works fine, and generates exactly the same logic.  But
you've pointed out something about VHDL that disturbs me.  The syntax
changes on the fly.  "WHEN" behaves what, four different ways?  It's
bizarre.  I've still got a lot to learn, anyway.

Quote:
> > I'm fitting this to a Cypress CY37128 PLD, so the issues aren't
> > quite the same as if I were doing it for an FPGA, which I think is your
> > concern.

> Understoood. It is different, I guess. I'd still be leery of telling
> the synth that I wanted to do arithmetic.

I guess I'm not understanding your concern.  It's dirt-simple
combinational logic to me.  If the compiler tried to do something fancy
with it then I'd REALLY be disturbed.  I've already had to do the
"attribute synthesis_off" thing on a multiplexer to keep the compiler
from minimizing itself into a corner.  It reminds me of writing low-
level hardware drivers in 'C' that the compiler optimizes so well that
they don't work :).

--

Intelligent Sensors
Sandia National Laboratories
Albuquerque, New Mexico, USA



Wed, 14 Jul 2004 06:17:46 GMT  
 Don't Care in a with...select?


Quote:


> > > Well, I could have written "when cpu_addr(4) = '0'" but the logic is the
> > > same.

> > Actually, you can't (at least I don't think so).  That would take an
> > if-then-else sort of thing.  I believe all the "when"s have to be on
> > the same variable/range.

> Actually, it works fine, and generates exactly the same logic.

Yikes!  I was thinking about the case-when sequential construct.  
I try to stay away from the concurrent constructs tor things
other than tristate drivers.  After a year trying to avoid
processes, I found them to be my dear friend.  

Quote:
> But
> you've pointed out something about VHDL that disturbs me.  The syntax
> changes on the fly.  "WHEN" behaves what, four different ways?  It's
> bizarre.  

So does "others", but that's language for ya!

Quote:
> I've still got a lot to learn, anyway.

Don't we all. I don't pretend to be an expert.  I learn by
getting slapped down.  ;-)  

Quote:
> > > I'm fitting this to a Cypress CY37128 PLD, so the issues aren't
> > > quite the same as if I were doing it for an FPGA, which I think is your
> > > concern.

> > Understoood. It is different, I guess. I'd still be leery of telling
> > the synth that I wanted to do arithmetic.

> I guess I'm not understanding your concern.  It's dirt-simple
> combinational logic to me.

Sure, but programs aren't humans.  They match patterns.  The way
to get the logic *you* want is to lay *big* hints to the
synthesizer. In this particular instance you're hinting to the
compiler that you want an adder.  Perhaps some are smart enough
to understand that that's not what you wanted, at least in this
compiler release.  My point is that you really need to instruct
the compiler what you want built.  This is especially true with
synthesizable VHDL.  The compiler isn't prescient.

Quote:
> If the compiler tried to do something fancy
> with it then I'd REALLY be disturbed.

Be prepared to be disturbed!

Quote:
> I've already had to do the
> "attribute synthesis_off" thing on a multiplexer to keep the compiler
> from minimizing itself into a corner.

You've already been "disturbed".  ;-)

There is a reason you had to do this.  It's best to learn that
reason and avoid it.  I get nervous when I have to resort to
instructing the compiler to do unnatural acts.  Sometimes it's
necessary, but I think long and hard before I do it.  Next year
the reasons may not be so clear.  Next year the issue may bite me
even harder when I've forgotten why I did the unnatural.

Quote:
> It reminds me of writing low-
> level hardware drivers in 'C' that the compiler optimizes so well that
> they don't work :).

That's why I only do assembler. If anything is needed above bit-
banging, get me a programmer. ;-)

----
  Keith



Wed, 14 Jul 2004 11:25:46 GMT  
 
 [ 13 post ] 

 Relevant Pages 

1. don't care the dryers strongly, mould them partly

2. don't care the dryers strongly, mould them partly

3. don't care the dryers strongly, mould them partly

4. Testing for unknowns or don't cares

5. Don't care states in decoders

6. Don't cares in expressions

7. Don't care in VHDL ???

8. How to deal with Don't cares

9. don't care in vhdl..

10. UnInit, Weak Unknown, Don't Care Signals

11. Don't cares in std_logic_vector

12. Don't care for integer?

 

 
Powered by phpBB® Forum Software