Xilinx ViewLogic package and simulating VHDL 
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 Xilinx ViewLogic package and simulating VHDL


We recently baught the Xilinx Viewlogic extended  package (DS-VLS-EXT)
from Xilinx, because we want to use VHDL to target the Xilinx FPGAs.

We were promised that we could both simulate and synthesize VHDL.

Synthesizing VHDL is working, but I'm not able to simulate VHDL. My
ViewLogic license explicitly says that VHDL simulation is possible,
but neither the local Xilinx representatives nor ViewLogic can tell me
how I should simulate VHDL with this package.

So does anybody out there know if VHDL simulation is possible with
this package and better yet how to do it ?

Fri, 26 Feb 1999 03:00:00 GMT  
 [ 1 post ] 

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