Multiple VHDL architectures under Xilinx WebPack ISE 4 project navigator 
Author Message
 Multiple VHDL architectures under Xilinx WebPack ISE 4 project navigator

Hi,

does anybody of you hard working people know a way how to organize
different architectures for a single entity within one WebPack
project? I've tried to use configurations and was looking for an
option for selecting the top entity/configuration name that has to be
used by synthesis, but nothing fit.
Please, let me know if you have an idea.

Thanks a lot,

Roman



Tue, 08 Feb 2005 20:55:35 GMT  
 Multiple VHDL architectures under Xilinx WebPack ISE 4 project navigator

Hi Roman

Personnally I am using a basic method which is working fine with
dev system I have used or curently used like ISE
 doing a design configuration through constant value
like this
entity test is
    Port (      ...........
          );
end test;

architecture Behavi{*filter*}of test is
 constant implement_case : integer := 0 ;
begin
    commun :process (clk,reset)
                .
                .
        end process ;
    case0: if (implement_case = 0) generate
     case00 :process (clk,reset)
                .
                .
             end process;
    end generate;
    case1: if (implement_case  = 1) generate
      case10: process (clk)
                .
                .
             end process;
    end generate;
    case2: if (implement_case  = 2) generate
     case20:process (clk,reset)
               .
               .
            end process;
     end generate;
   end Behavioral;

if you need more insight send me a post
regards

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Wed, 09 Feb 2005 04:32:37 GMT  
 
 [ 2 post ] 

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