of Alliance 1.2, a VLSI CAD System 
Author Message
 of Alliance 1.2, a VLSI CAD System

         *   ANNOUNCEMENT OF ALLIANCE RELEASE 1.2   16 Aug 93 *

A SPARC,LINUX and DEC version of the public domain ALLIANCE VLSI/CAD
system is now available at:

ftp.ibp.fr []           in /ibp/softs/masi/alliance
ftp-masi.ibp.fr []     in /pub/cao-vlsi/alliance
cao-vlsi.ibp.fr []     in /pub/alliance

ALLIANCE is a complete set of CAD tools and portable libraries for teaching
digital VLSI design in universities. It includes a VHDL compiler and
simulator, logic synthesis tools, automatic place and route, etc...
ALLIANCE is the result of a ten years effort at Universite Pierre et
Marie Curie (PARIS 6, FRANCE)

ALLIANCE is totally free, under the terms of the GNU General Public License.
It includes C source files and on-line english documentation (UNIX man)

The two main improvements over the release 1.1 are:

1) A hierarchical makefile allows to compile and install separately each
   ALLIANCE tool.
   The disk space required to compile and install the full ALLIANCE
   package is about 50 megs.
   The VHDL compiler and simulator ASIMUT requires only 3 megs.

   The source distribution is 32 Megs of which 14 Megs are sources.
   The rest is data files and documentations.
   Compiled on sparc (SunOS 4.1.1), this will give 9 megs of binaries.
   Compiled on dec (Ultrix 4.3), this will give 11 megs of binaries.
   Compiled on pc (linux-SLS 1.02), this will give 11 megs of binaries.

2) The release 1.2 has been succesfully compiled with the GNU gcc
   compiler. The full alliance package can now run on SPARC, LINUX
   and DEC architectures.

ALLIANCE 1.2 release contains the same tools and portable libraries
as the release 1.1, with few bugs fixed, thanks to several ALLIANCE
users, not limited to:

The ALLIANCE 1.2 release contains a complete tutorial: It allows to
design the 4 bits AMD2901 processor, from the VHDL specification to
the GDSII layout, using the ALLIANCE portable standard cell library.


The next release, ALLIANCE 2.0, will be distributed around december 93.

ALLIANCE 2.0 will contains several new advanced tools and libraries:
ALLIANCE 1.2 was dedicated to standard cell designs. ALLIANCE 2.0 will
contains tools and libraries for high complexity, optimized circuits:

* several parameterized CMOS generators:
    - RAGE static RAM generator
    - GROG high speed ROM generator
    - RSA  fast adder generator
    - BSG  barrel-shifter generator
    - AMG  pipelined multiplier generator
    - RFG  multi-ports register file generator

* the data-path compiler FITPATH for high performance and high density
  circuits (including a dedicated cell library)

* The timing analyser EXTASE with MOTIF interface.

* The procedural layout de{*filter*} GENVIEW allows to develop easily new
  portable generators or custom blocks.

* The Finite State Machine Synthesiser SYF and the net-list optimizer
  NETOPTIM allow to design high complexity controllers.

* The new, faster, symbolic layout editor GRAAL with MOTIF interface.

The ALLIANCE 2.0 release will provide a more ambitious tutorial:
The design of the 32 bits DLX microprocessor (PATTERSON & HENNESSY)
from the VHDL specification to the GDSII layout, using the ALLIANCE
data-path compiler and logic synthesis tools.


Sun, 18 Feb 1996 22:38:38 GMT  
 [ 1 post ] 

 Relevant Pages 

1. Upgrade to Alliance 3.0 CAD VLSI software

2. Alliance CAD 3.0, How to configure Genlib?

3. How to install Alliance CAD for Linux?

4. Q: Alliance 3.0 CAD tool installed an Linux

5. Help with VLSI CAD Engineering

6. Help with VLSI CAD Engineering

7. New Anonymous FTP site for VLSI/CAD Engineers.

8. Help with VLSI CAD Engineering

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