IEEE 1364 Verilog PLI-TSC Request for Enhancements, Errata 
Author Message
 IEEE 1364 Verilog PLI-TSC Request for Enhancements, Errata

Verilog Pli Users,

  I have been asked to chair a Pli Technical Subcommitee (Pli TSC)
charged with correcting errors, resolving ambiguities, and considering
enhancements to the Pli portion (Sections 17-23 and Annexes D and E)
of the Verilog IEEE 1364-1995 Specification.

  As our group will be handling both errata and enhancement requests,
please mark your message as to which category you feel it falls into.
We will give each message received a unique id.  If you put multiple
requests into you mail, please be sure to enumerate them, and mark

We may set up an official email address in the future, but this should
work for now.

  At our next meeting (Monday, December 9) , and at following meetings
we will start to consider and respond to requests submitted to us.


Andrew T. {*filter*}              Synopsys Inc.             (415)528-4960
Andrew T. {*filter*}              Synopsys Inc.             (415)528-4960

Fri, 21 May 1999 03:00:00 GMT  
 [ 1 post ] 

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