I'm using (clock'event and clock = '1') in my code, because I believe
that this is more portable, but I'd much rather use rising_edge, as
it's much easier to read (and type!).

Thanks,
Allan.

Hi,
    We had a similar discussion a few months back, we had a broader look
at most of the main stream tools - Synthesis, Simulation, & Formal
Verification. All of them seem to support it. We started recommanding
the usage of this construct within our company b'cos as you have
rightly said,

1.> It is more concise and clear

also

2.> It detects the exact rising edge and not a transaction from say "X"
to "1" which would be the case with the other construct.

Kind Regards,
Srini

function rising_edge(signal s : std_ulogic) return boolean is
begin
        return (s'event and (to_x01(s)='1') and (to_x01(s'last_value) = '1'));
end

So the question is rather if a particular tool supports the above VHDL
constructs (like the last_value attribute) or not. I can't see any other
resons for this function not to work (provided you use have access to
the 1164 package). In any case, you can always define your own
rising_edge function and use when and where you like.

Regards,

Mats Olsson
Ericsson Mobile Data Design AB
Gothenburg, Sweden