How to avoid this Latch 
Author Message
 How to avoid this Latch

Hi all,

Please help me . I am sure the following statements will be inferred as
latches and will cause me trouble.during testing.

IF(dcnt >= 1) THEN
      dcnt <= dcnt - "0001" ;
  END IF;

But I want to keep the values unchanged in "dcnt"  if the condition is
false. how can I do this without inferring a latch..

thanks
Lijo



Sun, 11 Sep 2005 13:28:31 GMT  
 How to avoid this Latch

Quote:
> But I want to keep the values unchanged in "dcnt"  if the condition is
> false. how can I do this without inferring a latch..

Erm.. how exactly did you plan to 'hold' a value without using a flipflop,
latch, or other memory component? Or would a flipflip be ok?

Regards,

Pieter Hulshoff



Sun, 11 Sep 2005 15:24:27 GMT  
 How to avoid this Latch
Hello Lijo,
           If you have coded this piece of code, sensitive to the clock
edge, then flip flops will be inferred for this counter. So you need no
worry about any latch inference. If you have coded the same as a
combinatorial logic, then register this value with respect to the clock
and then use the registered value for the else condition. By this way,
you can avoid latch getting inferred.

Anbudan,
Anand~


Quote:
> Hi all,

> Please help me . I am sure the following statements will be inferred as
> latches and will cause me trouble.during testing.

> IF(dcnt >= 1) THEN
>       dcnt <= dcnt - "0001" ;
>   END IF;

> But I want to keep the values unchanged in "dcnt"  if the condition is
> false. how can I do this without inferring a latch..

> thanks
> Lijo

--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG


Sun, 11 Sep 2005 17:36:28 GMT  
 How to avoid this Latch

Quote:

> IF(dcnt >= 1) THEN
>       dcnt <= dcnt - "0001" ;
>   END IF;

Eurgh - yeah, that'd would cause a latch, you haven't specified what the
system is meant to do when dcnt < 1, and it's level sensitive (to dcnt). I
would probably describe present and next state variables and use a
separate process to make the values change on the rising edge, which would
infer a flip-flop. (I'm assuming these terms are familiar to you, if not
you'll have to revise some digital electronics before going any further).

Try something like:
architecture demo of some_entity is
        signal this_dcnt, next_dcnt : integer;
begin
seq:process(clk) is
begin
        if rising_edge(clk) then
                this_dcnt <= next_dcnt;
        end if;
end process seq;

other:process(this_dcnt) is
begin
        if (this_dcnt >= 1) then
                next_dcnt <= this_dcnt - 1;
        else
                next_dcnt <= this_dcnt;
        end if;
end process other;
end architecture;

Quote:

> thanks
> Lijo

Also you might want to think a little bit about which newgroups you are
targeting with your question rather than bombarding 6 or 7 or them,

Hope this helps,

Andrew



Sun, 11 Sep 2005 20:43:35 GMT  
 How to avoid this Latch


Quote:
> Hi all,

> Please help me . I am sure the following statements will be inferred as
> latches and will cause me trouble.during testing.

> IF(dcnt >= 1) THEN
>       dcnt <= dcnt - "0001" ;
>   END IF;

> But I want to keep the values unchanged in "dcnt"  if the condition is
> false. how can I do this without inferring a latch..

Describe what you do expect it to do, and someone might suggest something.

Since you are storing back into dcnt, I don't think there is any other way.

If you store into a different variable, it could infer a MUX instead.

I prefer to write structural model Verilog, where this problem doesn't
occur.

-- glen



Mon, 12 Sep 2005 04:50:17 GMT  
 
 [ 5 post ] 

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