Problems with to_integer 
Author Message
 Problems with to_integer

Hi,

I am trying the following

    uns_vec := unsigned (SignalCount);
    counter := TO_INTEGER(uns_vec);

I keep getting the following ERROR:  to_integer can not have such
operands in this context.

Anyone have any clue? (using ISE 5)

STeve



Thu, 13 Oct 2005 15:42:46 GMT  
 Problems with to_integer
Signal Count is a Std_Logic_Vector..

Or is there another way to index a Vector array without converting to
integer?

eg:

    if (NetData(counter) = '1') then
     Data(counter) := '0';
    end if;

Steve

Quote:

> Hi,

> I am trying the following

>     uns_vec := unsigned (SignalCount);
>     counter := TO_INTEGER(uns_vec);

> I keep getting the following ERROR:  to_integer can not have such
> operands in this context.

> Anyone have any clue? (using ISE 5)

> STeve



Thu, 13 Oct 2005 15:46:34 GMT  
 Problems with to_integer

Quote:

>> Hi,

>> I am trying the following

>>     uns_vec := unsigned (SignalCount);
>>     counter := TO_INTEGER(uns_vec);

>> I keep getting the following ERROR:  to_integer can not have such
>> operands in this context.

>> Anyone have any clue? (using ISE 5)

>> STeve

Your code looks OK.  Here is a complete modelt aht compiled OK
You need the "use ieee.numeric_std.all;"

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity x is
end entity x;

architecture y of x is
  signal SignalCount : std_logic_vector(7 downto 0);
  signal uns_vec : unsigned (7 downto 0);
  signal counter : natural;
begin  -- architecture y
   uns_vec <= unsigned (SignalCount);
    counter <= TO_INTEGER(uns_vec);
end architecture y;
--
%vcom -93 test.vhd
Model Technology ModelSim SE vcom 5.7b Compiler 2003.02 Feb  1 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_std
-- Compiling entity x
-- Compiling architecture y of x
%
---------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------



Fri, 14 Oct 2005 02:34:58 GMT  
 Problems with to_integer
Thanks..  I figured it out..

I was using use IEEE.STD_LOGIC_ARITH.ALL which I guess causes a problem with the
to_integer function.

Thanks again

Steve

Quote:


> >> Hi,

> >> I am trying the following

> >>     uns_vec := unsigned (SignalCount);
> >>     counter := TO_INTEGER(uns_vec);

> >> I keep getting the following ERROR:  to_integer can not have such
> >> operands in this context.

> >> Anyone have any clue? (using ISE 5)

> >> STeve

> Your code looks OK.  Here is a complete modelt aht compiled OK
> You need the "use ieee.numeric_std.all;"

> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
> entity x is
> end entity x;

> architecture y of x is
>   signal SignalCount : std_logic_vector(7 downto 0);
>   signal uns_vec : unsigned (7 downto 0);
>   signal counter : natural;
> begin  -- architecture y
>    uns_vec <= unsigned (SignalCount);
>     counter <= TO_INTEGER(uns_vec);
> end architecture y;
> --
> %vcom -93 test.vhd
> Model Technology ModelSim SE vcom 5.7b Compiler 2003.02 Feb  1 2003
> -- Loading package standard
> -- Loading package std_logic_1164
> -- Loading package numeric_std
> -- Compiling entity x
> -- Compiling architecture y of x
> %
> ---------------------------------------------------------------------------
> Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830

> Author of following textbooks:
> * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> 0-9705394-2-8
> * Component Design by Example ",  2001 isbn  0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
> ------------------------------------------------------------------------------



Fri, 14 Oct 2005 02:40:47 GMT  
 Problems with to_integer
Hi Stephen!

Quote:
> I was using use IEEE.STD_LOGIC_ARITH.ALL which I guess causes a problem with the
> to_integer function.

I have seen such behavior last week. Cadence Leapfrog uses a different
IEEE.STD_LOGIC_ARITH than Synopsys Design Analyzer (both some older
versions). The result: compilation & simulation was running fine, but
synthesis did not.

With IEEE.Numeric.Std I've got never problems. -> It seems to be, that
this library is not so different between different tools (and different
versions).

Ralf



Fri, 14 Oct 2005 03:15:28 GMT  
 Problems with to_integer
use numeric_std.  It is an ieee standard and should behave the same on all tools.
std_logic_arith is not a standard, and as you have found, the implementations vary
from vendor to vendor.  It also contains some inconsistencies that will cause you
grief if you try to mix signed and unsigned types.

Quote:

> Hi Stephen!

> > I was using use IEEE.STD_LOGIC_ARITH.ALL which I guess causes a problem with the
> > to_integer function.

> I have seen such behavior last week. Cadence Leapfrog uses a different
> IEEE.STD_LOGIC_ARITH than Synopsys Design Analyzer (both some older
> versions). The result: compilation & simulation was running fine, but
> synthesis did not.

> With IEEE.Numeric.Std I've got never problems. -> It seems to be, that
> this library is not so different between different tools (and different
> versions).

> Ralf

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Sun, 16 Oct 2005 04:55:17 GMT  
 
 [ 6 post ] 

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