Abel conversion to VHDL 
Author Message
 Abel conversion to VHDL

Hi all,

I would be grateful to find any help concerning translation
between abel code to vhdl code. The context is about a design
writen in schematic and including some abel code architectures, in
Xilinx Foundation environment.
Regarding vhdl simulation (modelsim in this case) outside xilinx tools,
I naturalely asked
for a netlist conversion to vhdl code, but unfortunately, all abel codes
can only be simulated with  "xabelsim"  library, obviously not
interpreted
with such vhdl simulator.
As a consequence, it is actually not possible to simulate the design
functionaly,
but only after place and route.

Does anybody know any solution for this problematic ??

Thanks in advance.

Arnaud.



Tue, 12 Nov 2002 03:00:00 GMT  
 Abel conversion to VHDL
Use the Xilinx XPORT utility, in the 2.1 toolset.
Be warned that the output is every bit as good as
one would expect from an automatic translation tool.

XPORT translates ABEL or AHDL to Verilog or VHDL.

Quote:

>Hi all,

>I would be grateful to find any help concerning translation
>between abel code to vhdl code.



Wed, 13 Nov 2002 03:00:00 GMT  
 
 [ 2 post ] 

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