Quick question for Model Tech. experts: 
Author Message
 Quick question for Model Tech. experts:

Quick question for Model Tech. experts:

        How do you get around the problem of grouping individual signals to create and
        view a bus on Model Tech? If I start with a signal like counter(7 downto 0)
        and go through synthesis and place and route my final netlist now has eight
        individual signals representing counter(7 downto 0). Since Model Tech does      
        not have the capablity to group signals; what'd be an easy way to
        group them back together at the netlist level?

        Regards,
        Kayvon Irani
        Lear Astronics



Sat, 23 Jan 1999 03:00:00 GMT  
 Quick question for Model Tech. experts:

  Kayvon> Quick question for Model Tech. experts:

  Kayvon> How do you get around the problem of grouping individual
  Kayvon> signals to create and view a bus on Model Tech? If I start
  Kayvon> with a signal like counter(7 downto 0) and go through
  Kayvon> synthesis and place and route my final netlist now has eight
  Kayvon> individual signals representing counter(7 downto 0). Since
  Kayvon> Model Tech does not have the capablity to group signals;
  Kayvon> what'd be an easy way to group them back together at the
  Kayvon> netlist level?

I must second this. I was used to using a clustered signal in Vantage.
I do quite a bit of gate level VHDL simulation of Xilinx FPGAs and I
usually revert back to Vantage for this portion just because of this
feature. (I use ModelTech/Mentor for the RTL sim though...) I'd love
to be able to stay with the same QuickVHDL environment through the
whole design process.

  Kayvon> Regards, Kayvon Irani Lear Astronics

-- Scott Bilik



Mon, 25 Jan 1999 03:00:00 GMT  
 Quick question for Model Tech. experts:

Create a top level entity and architecture with the bus oriented
signal eg counter(7 downto 0). Then instantiate the synthesised
version as a component under this top level and manually join
counter(x) => counter_x in your port map



Tue, 26 Jan 1999 03:00:00 GMT  
 Quick question for Model Tech. experts:

Quote:

> I must second this. I was used to using a clustered signal in Vantage.
> I do quite a bit of gate level VHDL simulation of Xilinx FPGAs and I
> usually revert back to Vantage for this portion just because of this
> feature. (I use ModelTech/Mentor for the RTL sim though...) I'd love
> to be able to stay with the same QuickVHDL environment through the
> whole design process.

>   Kayvon> Regards, Kayvon Irani Lear Astronics

> -- Scott Bilik

Well, I think it is useless to say "me too", but I'm also frustrated by
this (and I'm also an old Vantage user !).

Could we do something to ask politely to add this feature ?

--

 DECT Design Engineer....................Phone....: (33) 92 96 11 19
 VLSI TECHNOLOGY France..................Fax......: (33) 92 96 11 01
 505, Route des Lucioles.................CellularP:
 Sophia Antipolis - 06560 Valbonne FRANCE



Sat, 30 Jan 1999 03:00:00 GMT  
 Quick question for Model Tech. experts:

Quote:

> Create a top level entity and architecture with the bus oriented
> signal eg counter(7 downto 0). Then instantiate the synthesised
> version as a component under this top level and manually join
> counter(x) => counter_x in your port map

Yes, of course, it's OK for top-level signals...

But when you want to look at internal busses, you can forget it !!!

--

 DECT Design Engineer....................Phone....: (33) 92 96 11 19
 VLSI TECHNOLOGY France..................Fax......: (33) 92 96 11 01
 505, Route des Lucioles.................CellularP:
 Sophia Antipolis - 06560 Valbonne FRANCE



Tue, 02 Feb 1999 03:00:00 GMT  
 
 [ 5 post ] 

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