resistor modelling 
Author Message
 resistor modelling

I have been working to model some resistors in vhdl
that could function as pull-up, pull-down, or just
plain resistors.  I have run into several problems.  
Has anyone worked on this problem yet?

I am including my non-functional attempt at this.  
Please let me know any suggestions.  Thanks.
--Lanne

entity RES is
      port (B1: inout std_logic;
            B2: inout std_logic);
end RES;

architecture RES of RES is
begin

   init : process
     variable C1, C2 : std_logic;
     begin
       if    (B1 = '1') then C2 := 'H';
       elsif (B1 = '0') then C2 := 'L';
       elsif (B1 = 'X') then C2 := 'W';
       end if;
       if    (B2 = '1') then C1 := 'H';
       elsif (B2 = '0') then C1 := 'L';
       elsif (B2 = 'X') then C1 := 'W';
       end if;

       if (C1 = 'H') or ( C1 = 'L') or ( C1 = 'W')
then B1 <= C1;
       end if;
       if (C2 = 'H') or ( C2 = 'L') or ( C2 = 'W')
then B2 <= C2;
       end if;

       wait;
   end process init;

   process (B1,B2)
     variable D1, D2 : std_logic;
   begin
     if (B1'event) then
       case B1 is
         when '0' => D2 := 'L';
         when '1' => D2 := 'H';
         when 'X' => D2 := 'W';
         when others => D2 := B1;
       end case;
       B2 <= D2;
     end if;
     if (B2'event) then
       case B2 is
         when '0' => D1 := 'L';
         when '1' => D1 := 'H';
         when 'X' => D1 := 'W';
         when others => D1 := B2;
       end case;
       B1 <= D1;
     end if;
   end process;

end RES;



Sun, 07 Feb 1999 03:00:00 GMT  
 resistor modelling

I have been working to model some resistors in vhdl
that could function as pull-up, pull-down, or just
plain resistors.  I have run into several problems.  
Has anyone worked on this problem yet?

I am including my non-functional attempt at this.  
Please let me know any suggestions.  Thanks.
--Lanne

entity RES is
      port (B1: inout std_logic;
            B2: inout std_logic);
end RES;

architecture RES of RES is
begin

   init : process
     variable C1, C2 : std_logic;
     begin
       if    (B1 = '1') then C2 := 'H';
       elsif (B1 = '0') then C2 := 'L';
       elsif (B1 = 'X') then C2 := 'W';
       end if;
       if    (B2 = '1') then C1 := 'H';
       elsif (B2 = '0') then C1 := 'L';
       elsif (B2 = 'X') then C1 := 'W';
       end if;

       if (C1 = 'H') or ( C1 = 'L') or ( C1 = 'W')
then B1 <= C1;
       end if;
       if (C2 = 'H') or ( C2 = 'L') or ( C2 = 'W')
then B2 <= C2;
       end if;

       wait;
   end process init;

   process (B1,B2)
     variable D1, D2 : std_logic;
   begin
     if (B1'event) then
       case B1 is
         when '0' => D2 := 'L';
         when '1' => D2 := 'H';
         when 'X' => D2 := 'W';
         when others => D2 := B1;
       end case;
       B2 <= D2;
     end if;
     if (B2'event) then
       case B2 is
         when '0' => D1 := 'L';
         when '1' => D1 := 'H';
         when 'X' => D1 := 'W';
         when others => D1 := B2;
       end case;
       B1 <= D1;
     end if;
   end process;

end RES;



Sun, 07 Feb 1999 03:00:00 GMT  
 resistor modelling

RASSP has a resistor model at
http://rassp.scra.org/information/public-vhdl/models/other.html
I haven't looked at it, but you could give it a try.

Quote:

> I have been working to model some resistors in vhdl
> that could function as pull-up, pull-down, or just
> plain resistors.  I have run into several problems.
> Has anyone worked on this problem yet?

> I am including my non-functional attempt at this.
> Please let me know any suggestions.  Thanks.
> --Lanne

> entity RES is
>       port (B1: inout std_logic;
>             B2: inout std_logic);
> end RES;

> architecture RES of RES is
> begin

>    init : process
>      variable C1, C2 : std_logic;
>      begin
>        if    (B1 = '1') then C2 := 'H';
>        elsif (B1 = '0') then C2 := 'L';
>        elsif (B1 = 'X') then C2 := 'W';
>        end if;
>        if    (B2 = '1') then C1 := 'H';
>        elsif (B2 = '0') then C1 := 'L';
>        elsif (B2 = 'X') then C1 := 'W';
>        end if;

>        if (C1 = 'H') or ( C1 = 'L') or ( C1 = 'W')
> then B1 <= C1;
>        end if;
>        if (C2 = 'H') or ( C2 = 'L') or ( C2 = 'W')
> then B2 <= C2;
>        end if;

>        wait;
>    end process init;

>    process (B1,B2)
>      variable D1, D2 : std_logic;
>    begin
>      if (B1'event) then
>        case B1 is
>          when '0' => D2 := 'L';
>          when '1' => D2 := 'H';
>          when 'X' => D2 := 'W';
>          when others => D2 := B1;
>        end case;
>        B2 <= D2;
>      end if;
>      if (B2'event) then
>        case B2 is
>          when '0' => D1 := 'L';
>          when '1' => D1 := 'H';
>          when 'X' => D1 := 'W';
>          when others => D1 := B2;
>        end case;
>        B1 <= D1;
>      end if;
>    end process;

> end RES;



Tue, 09 Feb 1999 03:00:00 GMT  
 resistor modelling

Quote:

>RASSP has a resistor model at
>http://rassp.scra.org/information/public-vhdl/models/other.html
>I haven't looked at it, but you could give it a try.

Take a look at my version of the resistor models and error injector models
at my ftp site:
  -- FTP site:   users.aol.com       /vhdlcohen/vhdl
  -- Web page:   http://members.aol.com/vhdlcohen/vhdl

--=============================================
-- Ben Cohen, "VHDL Coding Styles and Methodologies ",
--  ISBN 0-7923-9598-0  Kluwer Academic Publishers.
-- FTP site:   users.aol.com       /vhdlcohen
-- Web site: http://members.aol.com/VhdlCohen/Vhdl
-- Hughes Aircraft Co,  RE- R1/B507
-- 2000 East Imperial Hwy
-- El Segundo, Ca, 90245
-- (310) 334-7389,      fax: (310) 334-1749
--=============================================



Wed, 10 Feb 1999 03:00:00 GMT  
 
 [ 4 post ] 

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