Signal assignment mismatch with Aldec 5.1 problem 
Author Message
 Signal assignment mismatch with Aldec 5.1 problem

with Aldec 5.1 schematic I'm assigning

out_0 : out STD_LOGIC_VECTOR(9 downto 0);

to the bus

signal to_romx3 : STD_LOGIC_VECTOR (8 downto 0);

the result is

       out_0(0) => DANGLING_U2_out_0_0,
       out_0(1) => to_romx3(0),
       out_0(2) => to_romx3(1),
       out_0(3) => to_romx3(2),
       out_0(4) => to_romx3(3),
       out_0(5) => to_romx3(4),
       out_0(6) => to_romx3(5),
       out_0(7) => to_romx3(6),
       out_0(8) => to_romx3(7),
       out_0(9) => to_romx3(8),

while I would want

       out_0(0) => to_romx3(0),
       out_0(1) => to_romx3(1),
       out_0(2) => to_romx3(2),
       out_0(3) => to_romx3(3),
       out_0(4) => to_romx3(4),
       out_0(5) => to_romx3(5),
       out_0(6) => to_romx3(6),
       out_0(7) => to_romx3(7),
       out_0(8) => to_romx3(8),
       out_0(9) => DANGLING_U2_out_0_0,

How I could do this ??



Sun, 18 Jul 2004 15:47:14 GMT  
 Signal assignment mismatch with Aldec 5.1 problem


Quote:
> with Aldec 5.1 schematic I'm assigning

> out_0 : out STD_LOGIC_VECTOR(9 downto 0);

> to the bus

> signal to_romx3 : STD_LOGIC_VECTOR (8 downto 0);

> the result is

>        out_0(0) => DANGLING_U2_out_0_0,
>        out_0(1) => to_romx3(0),
>        out_0(2) => to_romx3(1),
>        out_0(3) => to_romx3(2),
>        out_0(4) => to_romx3(3),
>        out_0(5) => to_romx3(4),
>        out_0(6) => to_romx3(5),
>        out_0(7) => to_romx3(6),
>        out_0(8) => to_romx3(7),
>        out_0(9) => to_romx3(8),

> while I would want

>        out_0(0) => to_romx3(0),
>        out_0(1) => to_romx3(1),
>        out_0(2) => to_romx3(2),
>        out_0(3) => to_romx3(3),
>        out_0(4) => to_romx3(4),
>        out_0(5) => to_romx3(5),
>        out_0(6) => to_romx3(6),
>        out_0(7) => to_romx3(7),
>        out_0(8) => to_romx3(8),
>        out_0(9) => DANGLING_U2_out_0_0,

> How I could do this ??

select the bus wire properties and change to match your intended
connection (see segment description in help)


Mon, 19 Jul 2004 05:57:27 GMT  
 
 [ 2 post ] 

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