EIA Standard Logic Package Extensions 
Author Message
 EIA Standard Logic Package Extensions

If anybody is interested, here's some basic utilities that I wrote
that use the proposed EIA/IEEE standard logic representations.  Included
are overloads of the read/write operators for std_logic and std_logic_vector types,
and a std_logic_vector to unsigned integer converter.  While they may seem trivial
to a seasoned VHDL programmer, if the standard passes there be a need for routines
of this type, and maybe this posting will save somebody some time.

--------------------------------------------------------------------------
Alan Whittaker

M/S 62B-22                              PH# 407/724-7220
P.O. Box 883                            Fax 407/729-4960
Melbourne, FL 32902-0883

------------------ Cut Here ----------------------------------------------

use std.Textio.all;
use work.Std_Logic_1164.all;

Package EIA_extend is

-- I/O procedures for std_logic and std_logic_vector types.

        procedure write(l: inout line; value: in std_logic);
        procedure write(L: inout line; value: in std_logic_vector);

        procedure read(l: inout line; value: out std_logic);
        procedure read(L: inout line; value: out std_logic_vector);

-- Logic vector to unsigned integer conversion routine

        function To_uinteger( value: std_logic_vector ) return Integer;

end EIA_extend;

Package Body EIA_extend is

        procedure write(l: inout line; value: in std_logic) is
        begin
                case value is

                        when 'U' => write(l, Character'('U'));
                        when 'X' => write(l, Character'('X'));
                        when '0' => write(l, Character'('0'));
                        when '1' => write(l, Character'('1'));
                        when 'Z' => write(l, Character'('Z'));
                        when 'W' => write(l, Character'('W'));
                        when 'L' => write(l, Character'('L'));
                        when 'H' => write(l, Character'('H'));
                        when '-' => write(l, Character'('-'));
                        when others => write(l, Character'('X'));

                end case;

        end write;

   -- Write Std_Logic_Vector type

        procedure write(l: inout line; value: in std_logic_vector) is
        begin
                for i in value'high downto value'low loop
                        write(l,value(i));
                end loop;
        end write;

   -- Read Std_Logic type.

        procedure read(l: inout line;  value: out std_logic) is
                variable c: character;
        begin
              -- skip white space
                loop
                        read(l,c);
                        exit when ((c /= ' ') and (c /= CR) and (c /= HT));
                end loop;

                case c is

                        when 'U' => value := 'U';
                        when 'X' => value := 'X';
                        when '0' => value := '0';
                        when '1' => value := '1';
                        when 'Z' => value := 'Z';
                        when 'W' => value := 'W';
                        when 'L' => value := 'L';
                        when 'H' => value := 'H';
                        when '-' => value := '-';
                        when others => value := 'X';

                end case;

        end read;

    -- Read Std_Logic_Vector type

        procedure read(l: inout line; value: out std_logic_vector) is
        begin
                for i in value'high downto value'low loop
                        read(l, value(i));
                end loop;
        end read;

    -- Convert logic vector to unsigned integer

        function To_uinteger( value: std_logic_vector ) return Integer is
                variable result, factor: Integer;

             -- Unsigned dsp_vector to integer conversion
             -- Used in address decoding of RAMs
        begin
                result := 0;
                factor := 1;
                for i in value'low to value'high loop
                        if value(i) = '1' then
                                result := result + factor;
                        end if;
                        factor := factor * 2;
                end loop;
                return result;
        end To_uinteger;

end EIA_extend;



Tue, 10 May 1994 02:06:39 GMT  
 EIA Standard Logic Package Extensions
If anybody is interested, here's some basic utilities that I wrote
that use the proposed EIA/IEEE standard logic representations.  Included
are overloads of the read/write operators for std_logic and std_logic_vector types,
and a std_logic_vector to unsigned integer converter.  While they may seem trivial
to a seasoned VHDL programmer, if the standard passes there be a general need for
routines of this type, and maybe this posting will save somebody some time.

--------------------------------------------------------------------------
Alan Whittaker

M/S 62B-22                              PH# 407/724-7220
P.O. Box 883                            Fax 407/729-4960
Melbourne, FL 32902-0883

------------------ Cut Here ----------------------------------------------

use std.Textio.all;
use work.Std_Logic_1164.all;

Package EIA_extend is

-- I/O procedures for std_logic and std_logic_vector types.

        procedure write(l: inout line; value: in std_logic);
        procedure write(L: inout line; value: in std_logic_vector);

        procedure read(l: inout line; value: out std_logic);
        procedure read(L: inout line; value: out std_logic_vector);

-- Logic vector to unsigned integer conversion routine

        function To_uinteger( value: std_logic_vector ) return Integer;

end EIA_extend;

Package Body EIA_extend is

        procedure write(l: inout line; value: in std_logic) is
        begin
                case value is

                        when 'U' => write(l, Character'('U'));
                        when 'X' => write(l, Character'('X'));
                        when '0' => write(l, Character'('0'));
                        when '1' => write(l, Character'('1'));
                        when 'Z' => write(l, Character'('Z'));
                        when 'W' => write(l, Character'('W'));
                        when 'L' => write(l, Character'('L'));
                        when 'H' => write(l, Character'('H'));
                        when '-' => write(l, Character'('-'));
                        when others => write(l, Character'('X'));

                end case;

        end write;

   -- Write Std_Logic_Vector type

        procedure write(l: inout line; value: in std_logic_vector) is
        begin
                for i in value'high downto value'low loop
                        write(l,value(i));
                end loop;
        end write;

   -- Read Std_Logic type.

        procedure read(l: inout line;  value: out std_logic) is
                variable c: character;
        begin
              -- skip white space
                loop
                        read(l,c);
                        exit when ((c /= ' ') and (c /= CR) and (c /= HT));
                end loop;

                case c is

                        when 'U' => value := 'U';
                        when 'X' => value := 'X';
                        when '0' => value := '0';
                        when '1' => value := '1';
                        when 'Z' => value := 'Z';
                        when 'W' => value := 'W';
                        when 'L' => value := 'L';
                        when 'H' => value := 'H';
                        when '-' => value := '-';
                        when others => value := 'X';

                end case;

        end read;

    -- Read Std_Logic_Vector type

        procedure read(l: inout line; value: out std_logic_vector) is
        begin
                for i in value'high downto value'low loop
                        read(l, value(i));
                end loop;
        end read;

    -- Convert logic vector to unsigned integer

        function To_uinteger( value: std_logic_vector ) return Integer is
                variable result, factor: Integer;

             -- Unsigned dsp_vector to integer conversion
             -- Used in address decoding of RAMs
        begin
                result := 0;
                factor := 1;
                for i in value'low to value'high loop
                        if value(i) = '1' then
                                result := result + factor;
                        end if;
                        factor := factor * 2;
                end loop;
                return result;
        end To_uinteger;

end EIA_extend;



Mon, 09 May 1994 23:14:32 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. EIA/IEEE logic modeling standards

2. EIA Logic Package

3. Standard Logic Package

4. standard logic package

5. VHDL standard value logic packages

6. EIA 576 Standard

7. IEEE/EIA Package

8. Building "non-standard" standard extensions

9. Conversion from integer to standard logic vector

10. Find the smallest value of standard logic vector (7 downto 0)

11. bit, bit_vector to standard logic conversion

12. Translating an enumerated type signal into standard logic vector

 

 
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