type declarationsin synthesized VHDL netlist... 
Author Message
 type declarationsin synthesized VHDL netlist...

Try these settings:
vhdlout_single_bit = "VECTOR"
vhdlout_preserve_hierarchical_types = "VECTOR"

There is another variable to control the vector direction:
vhdlout???

Check all of the vhdl related variables with:
list -variables vhdlio



Tue, 20 Feb 2001 03:00:00 GMT  
 type declarationsin synthesized VHDL netlist...
Quote:

> Hi,

> I had a vhdl design using which I obtained a synthesized netlist from the
> Synopsys DC. Now, the DC makes up a lot of user defined data types and
> uses them in the netlist. e.g.

> ------- snipped netlist ---------
> library IEEE;

> use IEEE.std_logic_1164.all;

> package CONV_PACK_cla is

> -- define any necessary types
> type typeId_0 is array (31 downto 0) of std_logic;
> type typeId_1 is array (31 downto 0) of std_logic;
> type typeId_17 is array (3 downto 0) of std_logic;
> type typeId_18 is array (3 downto 0) of std_logic;
> .......
> .......
> end CONV_PACK_cla32_4;

> library IEEE;

> use IEEE.std_logic_1164.all;

> use work.CONV_PACK_cla.all;

> entity cla is
> .....
> .....

> ------- end netlist snip --------

> This kills me since I cannot use my original testbench on this netlist
> without writing a conversion package that carries out conversion
> from typeId_x to std_logic and vice versa.

> I guess vhdlout_dont_write_types would not help since it only suppresses
> types declared in the original vhdl.

> Does anyone have any idea how to get Synopsys VHDL writer not to
> define any data types on its own ?

The following line worked for me.

vhdlout_dont_write_types = "TRUE"

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Sat, 24 Feb 2001 03:00:00 GMT  
 
 [ 3 post ] 

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