Parent Signal Assignment inside Procedure? 
Author Message
 Parent Signal Assignment inside Procedure?

Hi

Is there anyway in VHDL to make signal assignment from procedure to
top-level signals declared in architecture?

E.g. "write_data" is made as procedure, so that it can be repeated to
drive
the top-level signals, as shown.

    ARCHITECTURE testbench OF foo_tb IS

       ...
      SIGNAL write_en : STD_LOGIC;
      SIGNAL addr     : STD_LOGIC_VECTOR(7 DOWNTO 0);
      SIGNAL data     : STD_LOGIC_VECTOR(7 DOWNTO 0);
        ...

      PROCEDURE write_data IS
        ...
      BEGIN
        WAIT FOR DELAY_1;

        write_en <= '1';
        addr <= "00001000";
        data <= "01010101";
          ...

        WAIT FOR DELAY_2;

        write_en <= '1';
        addr <= "00001010";
        data <= "11110000";
          ...

      END PROCEDURE write_data;

    BEGIN
      ...
      write_data;
      ...

    END ARCHITECTURE testbench;

But, my compiler complains that it can't drive signal from this
subprogram
and can't determine which process drives signal.

However, I prefer not having to declare every signal to be modified as
parameters to the procedure, given large number of signals to be driven.
And the procedure calls will be ungainly long lines.

      PROCEDURE write_data (
          SIGNAL write_en : OUT STD_LOGIC;
          SIGNAL addr     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          SIGNAL data     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
            ...   ) IS
       ...

      write_data(write_en, addr, data, ... );

How can I achieve it?  Is it even possible to do so in VHDL?

Thanks.

Regards
Hon-Chi

Sent via Deja.com
http://www.*-*-*.com/



Sun, 06 Jul 2003 12:56:55 GMT  
 Parent Signal Assignment inside Procedure?
Hi,

Quote:

> Hi

> Is there anyway in VHDL to make signal assignment from procedure to
> top-level signals declared in architecture?

  YES BUT *ONLY* if the procedure is declared (and hence used) within
a process.

Quote:
> E.g. "write_data" is made as procedure, so that it can be repeated to
> drive

>     ARCHITECTURE testbench OF foo_tb IS

>        ...
>       SIGNAL write_en : STD_LOGIC;

>       PROCEDURE write_data IS
>         ...

   This procedure is a concurrent one and hence can NOT modify global
signals (whicb are not in the formal parameters), if you declare this
within  a process then you could..

<SNIP>

Quote:
> But, my compiler complains that it can't drive signal from this
> subprogram
> and can't determine which process drives signal.

  Your compiler is right, here is an explanation:
Since this procedure has no formal parameters and is trying to modify
or "drive" a signal which is NOT in the formal parameter list, such a
transaction is ILLEGAL in VHDL. This is b'cos there is *no real owner*
for the signal driver (if in case this procedure is declared within a
process, then that process will be the *owner* for this signal driver)
and that's is why it is illegal. (VHDL needs to know all the drivers
for all the signals at compile-time).

For more (with a good example) visit:

http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#procedure_drivers

HTH,
Srini

--
Srinivasan Venkataramanan (Srini)
ASIC Design Engineer,
Chennai (Madras), India



Sun, 06 Jul 2003 14:52:07 GMT  
 Parent Signal Assignment inside Procedure?
Hi
Maybe this little test that I wrote to check XILINX RAM may help:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

library UNISIM;
use UNISIM.all;

ENTITY ck IS
END ;

ARCHITECTURE ck_0 OF ck is

component RAM32X1S
  port (D    : in std_ulogic;
        WE   : in std_ulogic;
        WCLK : in std_ulogic;
        A0   : in std_ulogic;
        A1   : in std_ulogic;
        A2   : in std_ulogic;
        A3   : in std_ulogic;
        A4   : in std_ulogic;
        O    : out std_ulogic);
end component;

signal sd     : std_logic := '0';
signal swe    : std_logic := '0';
signal swclk  : std_logic := '0';
signal sa     : std_logic_vector(4 downto 0) := (others => '0');
signal so     : std_logic;
signal soq    : std_logic;

begin

swclk <= not(swclk) after 30 ns;

u0 : RAM32X1S port map
(
  D    => sd,
  WE   => swe,
  WCLK => swclk,
  A0   => sa(0),
  A1   => sa(1),
  A2   => sa(2),
  A3   => sa(3),
  A4   => sa(4),
  O    => so
);
q : process(swclk)
begin
  if(swclk'event and swclk='1') then
    soq <= so;
  end if;
end process q;

stim : process
  procedure pr_nop is
  begin
    sd  <= 'Z';
    swe <= '0';
    sa  <= (others => 'Z');
    wait for 60 ns;
  end procedure pr_nop;

  procedure pr_wr
  (
    d : in std_logic;
    a : in std_logic_vector(4 downto 0)
  ) is
  begin
    sd  <= d;
    swe <= '1';
    sa  <= a;
    wait for 60 ns;
  end procedure pr_wr;

  procedure pr_rd
  (
    a : in std_logic_vector(4 downto 0)
  ) is
  begin
    sd  <= 'Z';
    swe <= '0';
    sa  <= a;
    wait for 60 ns;
  end procedure pr_rd;

begin
  --    sd   sa
  wait for 31 ns;
  pr_nop;
  pr_nop;
  pr_wr('1', "00000");
  pr_wr('1', "00001");
  pr_wr('0', "00010");
  pr_wr('0', "00011");

  pr_rd(     "00000");
  pr_rd(     "00001");
  pr_rd(     "00010");
  pr_rd(     "00011");

  pr_nop;
  pr_rd(     "10000");
  pr_wr('0', "10000");
  pr_wr('1', "10000");
  pr_rd(     "10000");
  pr_nop;
  pr_nop;

  wait;
end process stim;

end ck_0;



Quote:
> Hi

> Is there anyway in VHDL to make signal assignment from procedure to
> top-level signals declared in architecture?

> E.g. "write_data" is made as procedure, so that it can be repeated to
> drive
> the top-level signals, as shown.

>     ARCHITECTURE testbench OF foo_tb IS

>        ...
>       SIGNAL write_en : STD_LOGIC;
>       SIGNAL addr     : STD_LOGIC_VECTOR(7 DOWNTO 0);
>       SIGNAL data     : STD_LOGIC_VECTOR(7 DOWNTO 0);
>         ...

>       PROCEDURE write_data IS
>         ...
>       BEGIN
>         WAIT FOR DELAY_1;

>         write_en <= '1';
>         addr <= "00001000";
>         data <= "01010101";
>           ...

>         WAIT FOR DELAY_2;

>         write_en <= '1';
>         addr <= "00001010";
>         data <= "11110000";
>           ...

>       END PROCEDURE write_data;

>     BEGIN
>       ...
>       write_data;
>       ...

>     END ARCHITECTURE testbench;

> But, my compiler complains that it can't drive signal from this
> subprogram
> and can't determine which process drives signal.

> However, I prefer not having to declare every signal to be modified as
> parameters to the procedure, given large number of signals to be
driven.
> And the procedure calls will be ungainly long lines.

>       PROCEDURE write_data (
>           SIGNAL write_en : OUT STD_LOGIC;
>           SIGNAL addr     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
>           SIGNAL data     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
>             ...   ) IS
>        ...

>       write_data(write_en, addr, data, ... );

> How can I achieve it?  Is it even possible to do so in VHDL?

> Thanks.

> Regards
> Hon-Chi

> Sent via Deja.com
> http://www.deja.com/

Sent via Deja.com
http://www.deja.com/


Sun, 06 Jul 2003 16:00:44 GMT  
 
 [ 3 post ] 

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