vhdl, Process without wait statement

Process without wait statement

Author	Message
Paul Morga #1 / 6	Process without wait statement Hi, I designed a quick program in VHDL to automatically generate a text file for a testbench (stimulus file) to test exhaustively - there are 512 combinations. I managed this successfully, but since I'm obviously doing something VHDL wasn't really designed for I get a warning "Process without explicit or implicit wait statement - possible infinite loop.". The process doesn't have a sensitivity list or wait, since it only executes once to write the text file then I force it to stop with 'report "Generation complete" severity ERROR;'. I got around this using a 'wait for 1ns;' just before the report statement, but I wonder if anyone else uses VHDL for this sort of thing and how do you get around the problem? Thanks, Paul Morgan.
Mon, 28 Jul 2003 03:18:12 GMT

Egbert Molenkam #2 / 6	Process without wait statement Quote: > Hi, > I designed a quick program in VHDL to automatically generate a text file for > a testbench (stimulus file) to test exhaustively - there are 512 > combinations. > I managed this successfully, but since I'm obviously doing something VHDL > wasn't really designed for I get a warning "Process without explicit or > implicit wait statement - possible infinite loop.". Well not everyone will agree with this statement! Quote: > The process doesn't have a sensitivity list or wait, since it only executes > once to write the text file then I force it to stop with 'report "Generation > complete" severity ERROR;'. I got around this using a 'wait for 1ns;' just > before the report statement, but I wonder if anyone else uses VHDL for this > sort of thing and how do you get around the problem? But your problem is solved easily. Replace the report statement with a wait statement! e.g. PROCESS BEGIN your code wait; -- process waits forever END PROCESS; Egbert Molenkamp
Mon, 28 Jul 2003 03:52:46 GMT

VhdlCoh #3 / 6	Process without wait statement Quote: >I designed a quick program in VHDL to automatically generate a text file for >a testbench (stimulus file) to test exhaustively - there are 512 >combinations. >I managed this successfully, but since I'm obviously doing something VHDL >wasn't really designed for I get a warning "Process without explicit or >implicit wait statement - possible infinite loop.". >The process doesn't have a sensitivity list or wait, since it only executes >once to write the text file then I force it to stop with 'report "Generation >complete" severity ERROR;'. I got around this using a 'wait for 1ns;' just >before the report statement, but I wonder if anyone else uses VHDL for this >sort of thing and how do you get around the problem? >Thanks, >Paul Morgan. Yes, but I add a "wait;" that waits forever at the end of the process. -------------------------------------------------------------------------- ----------------------------------------- Ben Cohen ????Publisher, Trainer, Consultant ???(310) 721-4830 Author of following textbooks: * Component Design by Example ... a Step-by-Step Process Using ??VHDL with UART as Vehicle", ?2001 isbn ?0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 -------------------------------------------------------------------------- ------------------------------------------
Mon, 28 Jul 2003 04:29:11 GMT

x-gu #4 / 6	Process without wait statement Hi, In process, you need to have either sensitivity list or wait statement somewhere in the process. Quote: > Hi, > I designed a quick program in VHDL to automatically generate a text file for > a testbench (stimulus file) to test exhaustively - there are 512 > combinations. > I managed this successfully, but since I'm obviously doing something VHDL > wasn't really designed for I get a warning "Process without explicit or > implicit wait statement - possible infinite loop.". > The process doesn't have a sensitivity list or wait, since it only executes > once to write the text file then I force it to stop with 'report "Generation > complete" severity ERROR;'. I got around this using a 'wait for 1ns;' just > before the report statement, but I wonder if anyone else uses VHDL for this > sort of thing and how do you get around the problem? > Thanks, > Paul Morgan.
Mon, 28 Jul 2003 04:31:38 GMT

Paul Morga #5 / 6	Process without wait statement Quote: > Hi, > In process, you need to have either sensitivity list or wait statement somewhere > in the process. Thanks to all for the suggestions. I don't have a sensitivity list (or 'wait on' statement) because there are no signals outside the process for it to be sensitive to! The entity is empty and I'm using only variables - no signals at all, since its sole purpose is to produce a text file. I changed the 'report' to 'wait;' as suggested, so now the process suspends and the compiler tells me "Simulation has finished. No more test vectors to simulate." as I would expect - much better :-) Thanks again, Paul Morgan.
Mon, 28 Jul 2003 04:52:27 GMT

Chris G. Schneid #6 / 6	Process without wait statement Hi, just include a wait statement at the end. process begin <do something> -- done only once wait; -- wait forever end process; -- Chris
Mon, 28 Jul 2003 05:34:57 GMT

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