4-bit parallel shift register code 
Author Message
 4-bit parallel shift register code

Hi all,
does anybody here have any idea of where I can find the VHDL code for
a general 4-bit parallel shift register?
Thanx a lot:)


Thu, 14 Jul 2005 12:42:27 GMT  
 4-bit parallel shift register code

Quote:

> Hi all,
> does anybody here have any idea of where I can find the VHDL code for
> a general 4-bit parallel shift register?
> Thanx a lot:)

If you've forgotten how J, notK flip flops work you can look here:
<http://home.earthlink.net/~roadieroger/dl11.htm>
Code goes something like this:
-- shift4.vhd, like 74hc195
--
library ieee; -- maybe upper case
use ieee.std_logic_1164.all;

-- entity
entity SHIFT4 is
        port    (JP, KN, MRN, PEN, CLK : in std_logic;  -- asynchronous reset overrides all
                D : in std_logic_vector(3 downto 0);
                Q3N : out std_logic;
                Q : inout std_logic_vector(3 downto 0));
end entity SHIFT4;

-- architecture
architecture BEHAV of SHIFT4 is
begin
        STATE_CHANGE : process (CLK, MRN) is
        begin
                if (MRN = '0') then
                        Q(3 downto 0) <= "0000";
                        Q3N <= '1';
                elsif CLK'event and CLK = '1' then
                        if (PEN = '0') then
                                Q(3 downto 0) <= D(3 downto 0);
                                Q3N <= not(D(3));
                                else
                                Q(0) <= (not(Q(0)) and JP) or (Q(0) and KN);
                                Q(1) <= Q(0);
                                Q(2) <= Q(1);
                                Q(3) <= Q(2);
                                Q3N  <= not(Q(2));
                        end if;
                end if;
        end process STATE_CHANGE;
end architecture BEHAV;
--

Roadie Roger
<http://home.earthlink.net/~roadieroger/>



Fri, 15 Jul 2005 03:31:28 GMT  
 4-bit parallel shift register code

process...

    if sr_load='1' then
        sh_reg<=parallel_load;
    else
        sh_reg<= serial_in & sh_reg(3 downto 1);
    end if;

Quote:

> Hi all,
> does anybody here have any idea of where I can find the VHDL code for
> a general 4-bit parallel shift register?
> Thanx a lot:)

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Fri, 15 Jul 2005 22:04:26 GMT  
 4-bit parallel shift register code
Is that anything like the 74hc195r?
Cuz I got these ports instead:

input signals:
ck      : clock
cl      : inverted asynchronous clear
sl      : inverted synchronous load
j       : serial data in
kb      : serial data in
a,b,c,d : parallel data in

output signals:
qa,qb,qc,qd : parallel output
qdb         : inverted serial output

This is my draft entity:

library ieee;
use ieee.std_logic_1164.all;

entity hc195r is port(

  ck,cl,sl,j,kb:  in std_logic;
  qa, qb, qc, qd, qdb: out std_logic;

     )

Is it a correct entity?
How do I write the architecture?

Thanx a lot in advance.



Mon, 18 Jul 2005 09:39:50 GMT  
 4-bit parallel shift register code

[ re 74195 lookalike]

Quote:
> input signals:
> ck      : clock
> cl      : inverted asynchronous clear
> sl      : inverted synchronous load
> j       : serial data in
> kb      : serial data in
> a,b,c,d : parallel data in
> output signals:
> qa,qb,qc,qd : parallel output
> qdb         : inverted serial output

> This is my draft entity:

> library ieee;
> use ieee.std_logic_1164.all;
> entity hc195r is port(
>   ck,cl,sl,j,kb:  in std_logic;
>   qa, qb, qc, qd, qdb: out std_logic;
>      )
> Is it a correct entity?

You've missed a semicolon after the closing
parenthesis, and there should NOT be a
parenthesis BEFORE the closing parenthesis.

Apart from that detail, yes, it's correct;
but you get no marks for style.  Any interface
should always be extensively commented.  So (with my
ex-lecturer hat on, and as an engineer too) I would
prefer to see

... port (
  ck : in  std_logic;  -- shift clock, active on rising edge
  cl : in  std_logic;  -- active-low asynchronous clear
...

(I'm not sure the '195 is really RISING edge clocked.
But you have the data sheet, don't you?)

You might also prefer to rearrange the 4-bit output and
4-bit input as std_logic_vector(3 downto 0) bus ports,
depending on precisely what you've been asked to do.

Quote:
> How do I write the architecture?

First you look at some other examples from your notes.
Then you read some instructional information like a
text book - it makes more sense AFTER you've seen some
examples.  Then you take the code that Ray kindly gave
you and change it so it does the right things.  Note the
rather strange J/Kbar functionality of the serial input,
which will want some careful thought.  In particular you
will need to declare four internal signals in the
architecture, to represent the four flip-flops;  copy
those signals to the output ports with concurrent
assignment statements in the architecture body.

Take a look at the KnowHow section of our website for
lots of hints and tips about writing VHDL.

Then you need to write a test bench and simulate it.
That's a great deal harder than writing the model.

Then you take it away and try to synthesise it, and
discover you can't because it has an asynchronous load.
Lots of the old 74-series devices had that feature, but
it is a very poor match for modern FPGA technology and
design techniques.  So please ask your lecturer to choose
a more appropriate case study in future :-)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK

Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Mon, 18 Jul 2005 17:26:51 GMT  
 4-bit parallel shift register code

Quote:
> and there should NOT be a
> parenthesis BEFORE the closing parenthesis.

..^^^^^^^^^^^

oops, that'll be "there should NOT be a *semicolon* before
the final parenthesis".  <embarrassed cough>
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK

Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Mon, 18 Jul 2005 17:33:50 GMT  
 4-bit parallel shift register code
Hi all,

ok I wrote this entity and architecture but I don't know why it won't compile

--74hc195r.vhd

library ieee;
use ieee.std_logic_1164.all;

--entity

entity HC195R is port
 (
  CK   :  in std_logic; -- Clock
  CL   :  in std_logic; -- Inverted asynchronous clear
  SL   :  in std_logic; -- Inverted synchronous clear
  J, KB :  in std_logic; -- Serial data in

  I    :  in std_logic_vector(3 downto 0); -- Parallel data in
  Q    :  out std_logic_vector(3 downto 0); -- Parallel out
  QDB  :  out std_logic; --????
 );
 end entity HC195R;

--architecture

architecture BEHAVE of HC195R is
begin

 STATE_CHANGE : process (CK, CL) is
 begin  

  if CL = '0' then

     Q <= '0000';

  -- below concerns operations when CL = '1'

   elsif (SL = '1' ) then  

         if CK'event and CK = '1' then  -- rising edge clock

             if (J = '0' and KB = '0') then
                   Q(0) <= 0;
                   Q(1) <= Q(0);
                   Q(2) <= Q(1);
                   Q(3) <= Q(2);

             elsif (J = '0' and KB = '1') then
                   Q(0) <= Q(0);
                   Q(1) <= Q(0);
                   Q(2) <= Q(1);
                   Q(3) <= Q(2);

             elsif (J = '1' and KB = '0') then
                   Q(0) <= not Q(0);
                   Q(1) <= Q(0);
                   Q(2) <= Q(1);
                   Q(3) <= Q(2);

             else  Q(0) <= 1;
                   Q(1) <= Q(0);
                   Q(2) <= Q(1);
                   Q(3) <= Q(2);
             end if;

        elsif (CK ='0' or CK = '1') then -- when clock is 0 or 1 with SL = '1'
            Q <= Q;
        end if;

      else Q <= I;       -- when SL = '0'
      end if;

 end if;  

end process STATE_CHANGE;
end architecture BEHAVE;

Can anyone tell me what's wrong with the code?

Thanx a lot :)
Sara



Thu, 21 Jul 2005 19:06:11 GMT  
 4-bit parallel shift register code
Hi Sara,

Quote:

> (snip)
> entity HC195R is port
> (snip)
>   QDB  :  out std_logic; --????

This line contains a syntax error. Leave out the ";" after the last port
signal.

Quote:
>  );
>  end entity HC195R;
> (snip)
>   -- below concerns operations when CL = '1'

>    elsif (SL = '1' ) then

>          if CK'event and CK = '1' then  -- rising edge clock

>(snip)

The synchromous clear (SL) should be placed after the detection of the rising
clock edge, e.g.

if ASYNC_RESET='1' then
 Q <= '0';
elsif CK'event and CK='1' then
 if SL='1' then
  Q <= D;
 else
  Q <= '0';
 end if;
end if;

with kind regards,
Lars.
--
GnuPG public key:
http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.key



Thu, 21 Jul 2005 20:43:53 GMT  
 4-bit parallel shift register code
Hi all! :)

Here's what I wrote till now:

--74hc195r.vhd

library ieee;
use ieee.std_logic_1164.all;

--entity

entity HC195R is port
 (
  CK   :  in std_logic; -- Clock
  CL   :  in std_logic; -- Inverted asynchronous clear
  SL   :  in std_logic; -- Inverted synchronous clear
  J, KB :  in std_logic; -- Serial data in

  I    :  in std_logic_vector(3 downto 0); -- Parallel data in
  Q    :  out std_logic_vector(3 downto 0); -- Parallel out
  QDB  :  out std_logic --????
 );
 end entity HC195R;

--architecture

architecture BEHAVE of HC195R is
begin

 STATE_CHANGE : process (CK, CL) is
 begin  

  if CL = '0' then

     Q <= "0000";

  -- below concerns operations when CL = '1'

   elsif (SL = '1' ) then  

         if CK'event and CK = '1' then  -- rising edge clock

             if (J = '0' and KB = '0') then
                   Q(0) <= '0';
                   Q(1) <= Q(0);
                   Q(2) <= Q(1);
                   Q(3) <= Q(2);
                   --QDB <= ?

             elsif (J = '0' and KB = '1') then
                   Q(0) <= Q(0);
                   Q(1) <= Q(0);
                   Q(2) <= Q(1);
                   Q(3) <= Q(2);
                   --QDB <= ?

             elsif (J = '1' and KB = '0') then
                   Q(0) <= not Q(0);
                   Q(1) <= Q(0);
                   Q(2) <= Q(1);
                   Q(3) <= Q(2);
                   --QDB <= ?

             else  Q(0) <= '1';
                   Q(1) <= Q(0);
                   Q(2) <= Q(1);
                   Q(3) <= Q(2);
                   --QDB <= ?
             end if;

        elsif (CK ='0' or CK = '1') then -- when clock is 0 or 1 with SL = '1'
            Q <= Q;
            --QDB <= ?
        end if;

      else Q <= I; -- when SL = '0'
           --QDB <= ?
      end if;

 end if;  

end process STATE_CHANGE;
end architecture BEHAVE;

I'm still getting error messages in the architecture concerning these
lines and their similar lines:
Q(0) <= Q(0);
Q(1) <= Q(0);
Q(2) <= Q(1);
Q(3) <= Q(2);

Please tell me what's wrong with them.



Sat, 23 Jul 2005 03:31:33 GMT  
 4-bit parallel shift register code
Hi all! :) Ok,I figured it out...I needed to change the Q outputs to
buffer outs and it had no errors!Yay!Hehe :)
Now I need to write a test bench for it. Does anyone know how to do
it?
Thanx a lot! :)
Sara


Sun, 31 Jul 2005 05:46:01 GMT  
 4-bit parallel shift register code
Yes I am sure there are but I would suggest you have a crack at it first :-)

Quote:
> Hi all! :) Ok,I figured it out...I needed to change the Q outputs to
> buffer outs and it had no errors!Yay!Hehe :)
> Now I need to write a test bench for it. Does anyone know how to do
> it?
> Thanx a lot! :)
> Sara



Sun, 31 Jul 2005 06:16:16 GMT  
 4-bit parallel shift register code
Hi all!
Ok here's what I wrote till now:

--hc195r_tb.vhd

library ieee;
use ieee.std_logic_1164.all;

--entity

entity HC195R_tb is port
 (
 );
 end entity HC195R_tb;

--architecture

architecture TEST_BEHAVE of HC195R_tb is
signal cl,sl,j,kb,i,q0,q1,q2,q3,qdb:bit;

begin

 dut: entity work.hc195r(behave)
      port map ( cl,sl,j,kb,I,q0,q1,q2,q3,qdb);
 STIMULUS : process is
 begin  

     cl <= '0';
     wait for 50ns;
     cl <= '1';
     wait for 50ns;
     sl <= '0'; i <= i;
     wait for 50ns;
     sl <= '1';
     wait for 50ns;
     j <= '0'; k <= '0';
     wait for 50ns;
     j <= '0'; k <= '1';
     wait for 50ns;
     j <= '1'; k <= '0';
     wait for 50ns;
     j <= '1'; k <= '1';
     wait for 50ns;

  end process STIMULUS;
end architecture TEST_BEHAVE;

Is there anything missing in it?
Thanx a lot in advance.
Sara :)



Mon, 01 Aug 2005 00:34:57 GMT  
 4-bit parallel shift register code
Quote:

> Yes I am sure there are but I would suggest you have a crack at it first :-)


Surely a free test vector (or two) can't hurt :)
Quote:

> > Hi all! :) Ok,I figured it out...I needed to change the Q outputs to
> > buffer outs and it had no errors!Yay!Hehe :)
> > Now I need to write a test bench for it. Does anyone know how to do
> > it?
> > Thanx a lot! :)
> > Sara

Hi!
Your comment to SL says inverted synchronous clear, but the code
looks like it is SHIFT (HIGH), LOAD (LOW)

I have never seen

        elsif (CK ='0' or CK = '1') then -- when clock is 0 or 1 with SL = '1'
            Q <= Q;
            --QDB <= ?
        end if;

so I have no idea what the compiler will do with this.
I would suggest that you backup your file and then try to get one function
at a time working, CL, SL then J and KB.
This test bench claims you have errors.

Heres a start to a test bench:
--------------------------------------------------------------------------

-- hc195r_tb.vhd
-- Test Bench #1 for hc195r

library IEEE ;
use IEEE.STD_LOGIC_1164.ALL;

entity hc195r_tb is
end entity hc195r_tb;

architecture hc195r_test1 of hc195r_tb is

        signal J, KB, CL, SL, CK, QDB : std_logic;
        signal I, Q : std_logic_vector(3 downto 0);

        constant ATIME : time := 50 ns; -- note space after 50

begin
        dut: entity WORK.hc195r(BEHAVE)
        port map (CK, CL, SL, J, KB, I(3 downto 0), Q(3 downto 0), QDB);

        STIMULUS: process is
        begin

-- Test 1, SL is SHIFT (HIGH), LOAD (LOW), I(3 downto 0) is used for loading data
-- load some 1's to see if reset really works
        J <= '0'; KB <= '1'; CL <= '1'; SL <= '0'; I(3 downto 0) <= "1101";
        CK <= '0'; wait for ATIME; CK <= '1'; wait for ATIME;

-- now we'll do an asynchronous clear (CK high)
        J <= '1'; KB <= '1'; CL <= '0'; SL <= '0'; I(3 downto 0) <= "1101";
        wait for ATIME;

        J <= '1'; KB <= '1'; CL <= '1'; SL <= '0'; I(3 downto 0) <= "1101";
        wait for ATIME;

        if (Q(3 downto 0) /= "0000") then
            assert(false) report "ERROR, TEST 1: Q(3 downto 0) /= 0000" severity note ;
        end if ;
        if (QDB /= '1') then
            assert(false) report "ERROR, TEST 1: QDB /= 1" severity note ;
        end if ;

-- Test 2, Shift in a 1
        J <= '1'; KB <= '1'; CL <= '1'; SL <= '1'; I(3 downto 0) <= "0110";
        CK <= '0'; wait for ATIME; CK <= '1'; wait for ATIME;

        if (Q(3 downto 0) /= "0001") then
            assert(false) report "ERROR, TEST 2: Q(3 downto 0) /= 0001" severity note ;
        end if ;
        if (QDB /= '1') then
            assert(false) report "ERROR, TEST 2: QDB /= 1" severity note ;
        end if ;

-- Add another bunch of tests here

        ASSERT(FALSE) REPORT "hc195r Test is Done" SEVERITY NOTE ;

        wait;

        end process STIMULUS;

end architecture hc195r_test1;
------------------------------------------------------------------------------
Good Luck!
Roadie Roger
<http://home.earthlink.net/~roadieroger/index.htm>



Mon, 01 Aug 2005 03:15:33 GMT  
 4-bit parallel shift register code
Hi Sara,
Ok missing things would be that there are no tests within the test bench.
Check out the assert command and see if you can use it.
secondly you are using the type bit, does this concur with the types used in
the design under test ?
Your port map while I'm sure is correct for assignment by position would be
clearer if you specify each of the ports.
Having all of the ports in one line IMHO is messy and does not allow any
commentary.
None of the stimulus has any commentary as to what is going on and how to
check it.
A lot of your timing is the same time value, should you wish to change this
in the future you would have to go throughout the
code and change it, consider creating a procedure which would require only
one time change.
While its perfectly legal to put muiltiple assignments on one line IMHO it
looks messy, stops clear commentary and causes visual obfuscation of the
code structure, same for the signal declaration.
You will want to wave up the testbench to see whats happenning, there is a
simple trick how to display text in any waveform viewer (that is worth using
!) that will tell you instantly where you are in the testbench.
If your testbench has lots of tests think about creating procedures for each
of the tests.
While this doesn't have any busses its an idea to create independant
'watchers' that will report an illegal bus transaction.
There is no commentary as to what the testbench is going to test, is it
going to be testing an aardvaark, a coke machine or something else. Taking
this further who wrote the testbench, when was it written and are there any
special features that need to be
pointed out ?
Your testbench will keep running untill you hit the stop button. Consider
how to stop it in the testbench code.
It would be nice to report that the testbench has started and stopped to the
user of the testbench.
All of your inputs will be undefined at the start of the testbench, are you
sure you want this ?
Should you get out to the real world you may want to create 'real' test
vectors, consider looking at TEXTIO in your textbook to see how you can
create test vectors. If you do be careful regarding std_logic_vector.
There you go, I'm not going to tell you how to do it but using the comments
above and your text book you should be fine. Remember when it comes to the
real world you may not be the person who has to update your testbench so put
as much commentary in there to allow the next engineer to work out what you
have done.

Best Regards

Andre


Quote:
> Hi all!
> Ok here's what I wrote till now:

> --hc195r_tb.vhd

> library ieee;
> use ieee.std_logic_1164.all;

> --entity

> entity HC195R_tb is port
>  (
>  );
>  end entity HC195R_tb;

> --architecture

> architecture TEST_BEHAVE of HC195R_tb is
> signal cl,sl,j,kb,i,q0,q1,q2,q3,qdb:bit;

> begin

>  dut: entity work.hc195r(behave)
>       port map ( cl,sl,j,kb,I,q0,q1,q2,q3,qdb);
>  STIMULUS : process is
>  begin

>      cl <= '0';
>      wait for 50ns;
>      cl <= '1';
>      wait for 50ns;
>      sl <= '0'; i <= i;
>      wait for 50ns;
>      sl <= '1';
>      wait for 50ns;
>      j <= '0'; k <= '0';
>      wait for 50ns;
>      j <= '0'; k <= '1';
>      wait for 50ns;
>      j <= '1'; k <= '0';
>      wait for 50ns;
>      j <= '1'; k <= '1';
>      wait for 50ns;

>   end process STIMULUS;
> end architecture TEST_BEHAVE;

> Is there anything missing in it?
> Thanx a lot in advance.
> Sara :)



Mon, 01 Aug 2005 08:48:41 GMT  
 
 [ 14 post ] 

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