cycle simulation & event simulation 
Author Message
 cycle simulation & event simulation

Can anyone tell me what's the difference between cycle simulation and
event simulation?
There is a discussion about the Gate-level , behavioral, RTL simulation
and
Timing Simulation, functional simulation, I can't find it in my sea of
messages, can anyone tell me the date of the message? Thanks.

Sincerely Yours
Bing



Sat, 22 Sep 2001 03:00:00 GMT  
 cycle simulation & event simulation

Quote:

> Can anyone tell me what's the difference between cycle simulation and
> event simulation?
> There is a discussion about the Gate-level , behavioral, RTL simulation
> and
> Timing Simulation, functional simulation, I can't find it in my sea of
> messages, can anyone tell me the date of the message? Thanks.

> Sincerely Yours
> Bing

Hello Bing,

    If you have a circuit with clock as one of the inputs, and If your
circuit model gets evaluated
whenever there is a change on any of the input ports it is called event
simulation.

If you decide to evaluate the behaviour only on rising edge of clock and
then the evaluation
happens on each clock cycle, that is Cycle based simulation.

hope this clarifies,
thanks and regards,
Ravi
--



Mon, 24 Sep 2001 03:00:00 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. Cycle Simulation & Code Coverage

2. verilog simulation /bus-cycle models

3. Cycle Based Simulation

4. Q: Cycle based simulation: What, how, etc

5. cycle-based simulation, etc.

6. Vhdl cycled base simulation.

7. cycle-based simulation

8. Cycle Based Simulation

9. Simulation cycle

10. driver, projected waveform, simulation-cycle

11. C-based simulation faster than HDL-based simulation?

12. Job Posting: Simulation Support (Viewlogic/Simulation Group)

 

 
Powered by phpBB® Forum Software