VHDL Enhancements ('DRIVER) 
Author Message
 VHDL Enhancements ('DRIVER)

The 'DRIVER suggestion was aimed at modelling CMOS/nMOS pass transistor circuits
when using simple logic types (e.g. MVL4/7). Models for these devices would
typically pass values from one signal (A) to another (B) with a fixed delay. If
there are other processes driving the signal B then the pass transistor model
needs to be able to identify whether the events on B are ones it scheduled - since
these should not be passed back to A. I don't think this can be done without
a more complex logic type at the moment.

Further Suggestion:
Attributes could also be introduced to indicate how many drivers there are for a
signal and how many are active in any cycle e.g.:

   B'DRIVERS         -- The total number of drivers driving B.
   B'ACTIVE_DRIVERS  -- The total number of drivers active in this simulation
                        cycle.

This sort of information is usually stored by VHDL simulators - it just needs a
method for accessing it.

The aim of these suggestions is to enable complex models to be developed for
low level devices (for pass transitor circuits etc.), but using simple logic
types compatible with the simple models which form the bulk of any large
(silicon) design.

-------------------------------------------------------------------------------
Kevin Cameron         INMOS, 1000 Aztec West, Almondsbury, Bristol BS12 4SQ, UK
                      Tel: (UK) 0454 616 616 x364, Fax: 617 910



Mon, 01 Nov 1993 17:29:20 GMT  
 
 [ 1 post ] 

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