Q: Casting record data type 
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 Q: Casting record data type


As far  as a digital design  is concerned, any  VHDL data types should
have   its binary implementation    ,  to say  std_logic_vector.   For
instance,   in  Synopsys there     are   some functions     converting
integer/signed/unsigned  to (from) std_logic_vector.    But up to  the
moment, I could not find  a method to  cast record or enumeration data
type  to its binary counterpart.  To  make the question clear, I would
give an example below.

excerpt from vhdl code.
  type RRFunc  is (Nop, Add, Sub,
                   And, Or, Xor,
                   Seq, Sne, Slt, Sgt, Sge,
                   Lw, Sw, Sb, Lb, Lh, Sh,
                   Sll, Srl, Sle,
                   Movi2s, Movs2i); -- 23 enumerations without encoding

 type JtypeInstr is (OpRfe, OpJr, OpJalr, OpHalt); -- 4 enum. without
                                                   -- encoding

 type vec  is std_logic_vector ( 0 to 5);

 type instruction is
          opcode : RRFunc;
          immediate : vec;
          function  : JtypeInstr;
        end record;


An optimized VHDL logic  sythesizer may convert  RRFunc to 5 bits wide
bit vector, JtypeInstr  to  2bits and  vec  to 6bits, then  assign  an
appropriate enumeration  code to each   element.   Then I might   have
"instruction" wide 5+2+6=13 bits.

My questions are :
Given these variables as follows.

  variable RRFuncVar  : RRFunc;
  variable RRFuncVec  : std_logic_vector (0 to 4);

  variable NextInstr  : instruction;
  variable Memory     : std_logic_vector (0 to 12);

Is it possible to perform :
(1)    RRFunc := AnyConvFunction1 ( RRFuncVec);
(2)    RRFuncVec := AnyConvFunction2 (RRFunc);
(3)    NextInstr := AnyConvFunction3 (Memory);
(4)    Memory    := AnyConvFunction4 (NextInstr);

If it is possible, than what kind of functions are AnyConvFunction[1-4].

Any assistance is appreciated.
Eko Fajar
Dept. of Information Science
Kyushu Univ.


Tue, 09 Feb 1999 03:00:00 GMT  
 [ 1 post ] 

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