Shared Variable Requirements The Shared Variable Working Group of the IEEE DASC is developing a 
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 Shared Variable Requirements The Shared Variable Working Group of the IEEE DASC is developing a

set of requirements for the use of shared variables (SVs) in VHDL.  We would
appreciate user input from designers who currently use or plan to use
shared variables in their designs.  In particular we would like specific
information on:
    - what modeling problem is solved by the use of SVs and why it
       could not be accomplished by another mechanism
    - what impact concurrency has on the design and use of SVs i.e.
        does the current design envirnoment support concurrency, are
        specific synchronization mechanisms used for control, is there
        a stylistic limitation that prevents concurrent updates?
    - types of synchronization control do you think is required (why?)

Please send responses of general interest to the SV reflector:

If you would like to join the reflector, contact Steve Bailey, SVWG chair

or contact the SVWG requiremnts team:



Keywords:



Tue, 30 Jan 1996 22:29:06 GMT  
 
 [ 1 post ] 

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