orcad synthesis for simplepld 
Author Message
 orcad synthesis for simplepld

I'm new to using ORCAD (I have tried mailing them/using their notice board
with no response so far) - does anyone have any experience of using
the Express synthesis for simpleplds (actually GAL22V10)?
I have a little behavioural VHDL FSM which analyzes ok; when I try to build
it Express generates an error message telling me I have too many
product terms for a couple of rows. On inspecting the vhdl netlist
its generated, there are actually not many PTs in the expressions
its complaining about - well within the powers of a 22V10!
Is there a common user error which could generate this? Or is this
a known problem for which a patch is available?  (I have v. 7.1)

Thanks for any advice,

Graham Seaman



Sat, 27 Apr 2002 03:00:00 GMT  
 orcad synthesis for simplepld
Do not waste your time and money on OrCAD Express.



Quote:
> I'm new to using ORCAD (I have tried mailing them/using their notice
board
> with no response so far) - does anyone have any experience of using
> the Express synthesis for simpleplds (actually GAL22V10)?
> I have a little behavioural VHDL FSM which analyzes ok; when I try to
build
> it Express generates an error message telling me I have too many
> product terms for a couple of rows. On inspecting the vhdl netlist
> its generated, there are actually not many PTs in the expressions
> its complaining about - well within the powers of a 22V10!
> Is there a common user error which could generate this? Or is this
> a known problem for which a patch is available?  (I have v. 7.1)

> Thanks for any advice,

> Graham Seaman

Sent via Deja.com http://www.deja.com/
Before you buy.


Sun, 28 Apr 2002 03:00:00 GMT  
 orcad synthesis for simplepld

Quote:

> Do not waste your time and money on OrCAD Express.

Now there's a helpful answer!

Are the pins constrained?  The 22v10 has 10 product terms on the 'outside'
outputs and 16 on the center ones.  If you have, say 12 product terms,
there are four outputs that the equation can't be assigned to.

Quote:


> > I'm new to using ORCAD (I have tried mailing them/using their notice
> board
> > with no response so far) - does anyone have any experience of using
> > the Express synthesis for simpleplds (actually GAL22V10)?
> > I have a little behavioural VHDL FSM which analyzes ok; when I try to
> build
> > it Express generates an error message telling me I have too many
> > product terms for a couple of rows. On inspecting the vhdl netlist
> > its generated, there are actually not many PTs in the expressions
> > its complaining about - well within the powers of a 22V10!
> > Is there a common user error which could generate this? Or is this
> > a known problem for which a patch is available?  (I have v. 7.1)

> > Thanks for any advice,

> > Graham Seaman

> Sent via Deja.com http://www.deja.com/
> Before you buy.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://users.ids.net/~randraka


Sun, 28 Apr 2002 03:00:00 GMT  
 orcad synthesis for simplepld
:
: > Do not waste your time and money on OrCAD Express.
: >
:
: Now there's a helpful answer!
And I don't have any choice... but it sounds like there are well
known problems with it. What are they?

:
: Are the pins constrained?  The 22v10 has 10 product terms on the 'outside'
: outputs and 16 on the center ones.  If you have, say 12 product terms,
: there are four outputs that the equation can't be assigned to.
:
No, no pins constrained at all. 6 outputs are used, 2 registered with 3 PTs
each (none of the pts have more than 4 variables). These are the ones I
get the error messages for.
The rest are combinational and only need 1 pt. So its
clearly not a 'real' fitting problem. My guess is that maybe there's a
problem with the simplepld library - perhaps something I haven't included,
the documentation is very patchy. I guess I have to track down an Orcad user...

Graham



Mon, 29 Apr 2002 03:00:00 GMT  
 orcad synthesis for simplepld


Quote:
> I'm new to using ORCAD (I have tried mailing them/using their notice
board
> with no response so far) - does anyone have any experience of using
> the Express synthesis for simpleplds (actually GAL22V10)?
> I have a little behavioural VHDL FSM which analyzes ok; when I try to
build
> it Express generates an error message telling me I have too many
> product terms for a couple of rows. On inspecting the vhdl netlist
> its generated, there are actually not many PTs in the expressions
> its complaining about - well within the powers of a 22V10!
> Is there a common user error which could generate this? Or is this
> a known problem for which a patch is available?  (I have v. 7.1)

> Thanks for any advice,

> Graham Seaman

We have encountered a number of problems using OrCAD Express.  OrCAD
themselves admit that the synthesis engine they wrote was less than
perfect.  That's why they bolted in the Exemplar synthesis engine in
release 9.  They still use the homegrown synthesizer for simple PLDs
though.

We are working with Xilinx CPLDs and FPGAs.  The problems that we are
experiencing are mostly related to the interface between Capture and
Express, and the interface between Express and the Xilinx A2.1i tools.
We have problems passing constraints through, and we have found one bad
macro (XIL_M1\XC4000E\CB2CLE.EDN).

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.

Sent via Deja.com http://www.deja.com/
Before you buy.



Mon, 29 Apr 2002 03:00:00 GMT  
 orcad synthesis for simplepld
: > I have a little behavioural VHDL FSM which analyzes ok; when I try to
: build
: > it  Orcad Express generates an error message telling me I have too many
: > product terms for a couple of rows. On inspecting the vhdl netlist
: > its generated, there are actually not many PTs in the expressions
: > its complaining about - well within the powers of a 22V10!
: > Is there a common user error which could generate this? Or is this
: > a known problem for which a patch is available?  (I have v. 7.1)
: >
: > Thanks for any advice,
: >
: > Graham Seaman
: >

OK, I found the problem (with some help ;-). The error message itself
is misleading: its actually complaining because the registers used for
state bits in an FSM haven't been assigned pins [so ANY PTs would be too many
in this case]. This is because I went from a behavioural (case-statement)
style design for the FSM, and as far as I can see means that I can't use
this style of design for state machines going into PLDs and have to revert
to hand minimisation. Since this must be one of the most common applications
for PLDs, and since IIRC even ABEL used to be able to handle this, I'm now
curious about how common a problem this is. Is VHDL synthesis generally worse
than old ABEL/CUPL/Palasm synthesis?
Or is it just that little PLDs are so un{*filter*} that no-one bothers much
developing the tools?

Graham



Wed, 01 May 2002 03:00:00 GMT  
 orcad synthesis for simplepld
<snip>
Quote:
>curious about how common a problem this is. Is VHDL synthesis generally
worse
>than old ABEL/CUPL/Palasm synthesis?
>Or is it just that little PLDs are so un{*filter*} that no-one bothers much
>developing the tools?

Graham,
I suspect that this is an Orcadism.  Some years ago Orcad was held in high
regard, with a widely used product of good quality.  In the last 5 years,
since the belated introduction of their Windows product line, I've lost all
faith in their ability to deliver a useable piece of software, despite the
fact that their hearts may be in the right place.  Perhaps sooner or later
they may get their act together.  I haven't used version 9.  Version 7.1,
which you refer to, I found to be a complete disaster.

You could post your code, and I could run it through Exemplar, Synplify, or
Maxplus, and I'm sure it would come out fine.  Certainly as good as Abel.  I
don't do much PLD stuff, but I do have a little 5032 design that is written
in behavioural VHDL and synthesizes great with Synplify.

It really is too bad about Orcad.  In the last days of DOS, they ruled!

Tom Meagher
Houston TX

Quote:


>: > I have a little behavioural VHDL FSM which analyzes ok; when I try to
>: build
>: > it  Orcad Express generates an error message telling me I have too many
>: > product terms for a couple of rows. On inspecting the vhdl netlist
>: > its generated, there are actually not many PTs in the expressions
>: > its complaining about - well within the powers of a 22V10!
>: > Is there a common user error which could generate this? Or is this
>: > a known problem for which a patch is available?  (I have v. 7.1)
>: >
>: > Thanks for any advice,
>: >
>: > Graham Seaman
>: >

>OK, I found the problem (with some help ;-). The error message itself
>is misleading: its actually complaining because the registers used for
>state bits in an FSM haven't been assigned pins [so ANY PTs would be too
many
>in this case]. This is because I went from a behavioural (case-statement)
>style design for the FSM, and as far as I can see means that I can't use
>this style of design for state machines going into PLDs and have to revert
>to hand minimisation. Since this must be one of the most common
applications
>for PLDs, and since IIRC even ABEL used to be able to handle this, I'm now
>curious about how common a problem this is. Is VHDL synthesis generally
worse
>than old ABEL/CUPL/Palasm synthesis?
>Or is it just that little PLDs are so un{*filter*} that no-one bothers much
>developing the tools?

>Graham



Wed, 08 May 2002 03:00:00 GMT  
 
 [ 7 post ] 

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