Does the VHDL language support anything like Verilog's
"escaped" identifiers (eg. "\funky-name!!" ) ?

If not, is there a standard or commonly employed method
for dealing with port, instance, and signal names that
would otherwise be considered illegal VHDL identifiers ?

Suggestion, example:  
attribute RENAMED_NAME of SIG1 : signal is "5&&2p1##lala" ;
or something like this.

Any ideas ?

-----------

|> Does the VHDL language support anything like Verilog's
|> "escaped" identifiers (eg. "\funky-name!!" ) ?
|>
|> If not, is there a standard or commonly employed method
|> for dealing with port, instance, and signal names that
|> would otherwise be considered illegal VHDL identifiers ?
|>
|> Suggestion, example:  
|> attribute RENAMED_NAME of SIG1 : signal is "5&&2p1##lala" ;
|> or something like this.
|>
|> Any ideas ?
|>
|>
|>
|> -----------

VHDL 93 has this extension, e.g.

You simply encapsulate such an identifier in \ \ . If you need a backslash
inside the name, double it. These so called extended identifiers are
valid wherever identifiers are allowed in the language. Note that they
are case sensitive as well. Also, an extended identifier is different from
any basic identifier with the same character sequence, e.g. \FOO\ is not FOO.

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