vhdl and viewlogic problem 
Author Message
 vhdl and viewlogic problem

Hi newsgroup,
I have a simple (?) problem using VHDL and Viewlogic. After declaration of
an entity I use VHDL2SYM.EXE to create a symbol for ViewDraw. It works fine,
but I want to have an active low signal (signalname with overline) in my
schematic.
I have no idea how to realize it in VHDL . Any suggestions?


Sun, 02 Dec 2001 03:00:00 GMT  
 vhdl and viewlogic problem

Quote:

>Hi newsgroup,
>I have a simple (?) problem using VHDL and Viewlogic. After declaration of
>an entity I use VHDL2SYM.EXE to create a symbol for ViewDraw. It works
fine,
>but I want to have an active low signal (signalname with overline) in my
>schematic.
>I have no idea how to realize it in VHDL . Any suggestions?

VHDL, being a text-only language, has no way of indicating that a signal is
active low.  Some people like to create signal/variable names that indicate
that a signal is active low.  I use _l  (as in oe_l for an output enable).

Since the language doesn't have any way to indicate active low, the symbol
generator utility won't be able to put bars over signals.  Can you go in an
edit the symbol?  (Probably not, at least without breaking connectivity.)

-- a
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719

NY Knicks in '99:
"Ya gotta believe!"



Sun, 02 Dec 2001 03:00:00 GMT  
 vhdl and viewlogic problem
The label bar (label sense) in viewlogic alters the signal name, so you'll lose
connectivity if you change that.  Be careful using the label bar in schematics
for FPGAs, some of the tools don't like it.  The pin sense on the symbol is
just on the symbol, so you can go into the symbol editor and change that
(select the pin(s) and type pse on the command line).  Changing the pin sense
will put a bubble on the pin without changing the connectivity to the
underlying logic.

Quote:


> >Hi newsgroup,
> >I have a simple (?) problem using VHDL and Viewlogic. After declaration of
> >an entity I use VHDL2SYM.EXE to create a symbol for ViewDraw. It works
> fine,
> >but I want to have an active low signal (signalname with overline) in my
> >schematic.
> >I have no idea how to realize it in VHDL . Any suggestions?

> VHDL, being a text-only language, has no way of indicating that a signal is
> active low.  Some people like to create signal/variable names that indicate
> that a signal is active low.  I use _l  (as in oe_l for an output enable).

> Since the language doesn't have any way to indicate active low, the symbol
> generator utility won't be able to put bars over signals.  Can you go in an
> edit the symbol?  (Probably not, at least without breaking connectivity.)

> -- a
> ------------------------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719

> NY Knicks in '99:
> "Ya gotta believe!"

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://users.ids.net/~randraka


Sun, 02 Dec 2001 03:00:00 GMT  
 
 [ 3 post ] 

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