MaxPlus2 compiler problem 
Author Message
 MaxPlus2 compiler problem

I have a simple design in which I declare two output ports named cnt1
and cnt10, both std_logic_vector(3 downto 0).  The design compiles and
simulates fine with Cypress Warp (Aldec HDL), but Altera MaxPlus2 gives
the following error:

Duplicate pin name "cnt10"

When I change the name of the port from cnt10 to cnt2, the design
compiles without problem.

Can anyone tell me what's going on?

Eric W. Hansen
Thayer School of Engineering
Dartmouth College
Hanover, NH 03755-8000



Sun, 11 Sep 2005 01:07:10 GMT  
 MaxPlus2 compiler problem

Quote:

> Duplicate pin name "cnt10"

> When I change the name of the port from cnt10 to cnt2, the design
> compiles without problem.

> Can anyone tell me what's going on?

Sounds like a MaxPlus2 bug.
Perhaps this version only looks at the first four characters
of the port identifiers in some cases.

Consider using Altera's Leonardo or Quartus.

    -- Mike Treseler



Sun, 11 Sep 2005 02:27:19 GMT  
 MaxPlus2 compiler problem

Quote:
> I have a simple design in which I declare two output ports named cnt1
> and cnt10, both std_logic_vector(3 downto 0).  The design compiles and
> simulates fine with Cypress Warp (Aldec HDL), but Altera MaxPlus2 gives
> the following error:

> Duplicate pin name "cnt10"

> When I change the name of the port from cnt10 to cnt2, the design
> compiles without problem.

> Can anyone tell me what's going on?

MP2 might be naming the pins of cnt1 as cnt10, cnt11, cnt12, cnt13,
then looking at cnt10 as a duplicate (presumably before it does the
appending of bit numbers).

If renaming the pin works, that might be your best solution.

Cheers,
Martin

--

TRW Conekt, Solihull, UK
http://www.trw.com/conekt



Sun, 11 Sep 2005 17:18:32 GMT  
 
 [ 3 post ] 

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