(Altera) VITAL libraries 
Author Message
 (Altera) VITAL libraries

Altera Corporation seems to be having some difficulty
answering my question so I'm posting this to the general
readership in the hope that someone can shed some
light on this topic.  (I also apologize for the length
of the post.)

I'm interested in suppressing glitch messages that are
generated in the simulation monitor window while
simulating synthesized CPLD/FPGA parts.  While having the
simulation reveal glitches is useful under certain
circumstances, for my present purpose they are distracting
and tend to obscure warning messages that I'm really
interested in, such as timing violations.

************ What we're doing: ************
We are designing and simulating several boards that
use various devices from Altera's MAX and FLEX product
line.  The designs which are targeted to these devices
are written in VHDL and synthesized using the Exemplar
Galileo tool.   We use the MAX+plus II Compiler,
Version 7.22 4/14/97, to generate the binary device
programming data and VHDL structural output files
(.vho) for post synthesis simulation using Mentor's tools:

QuickHDL Pro FlexSim Integration v8.5_1.11
QuickSimII FlexSim Integration  v8.5_1.9
FlexSim  v8.5_1.6

************ What's happening: *************
When we generate the .vho files, we set MAX+plus to
generate SDF output files (.sdo) Version 2.1.  The
associated output (.vho) files are then VITAL compliant.
These .vho files reference cell primatives contained in a
(compiled) library called alt_vtl.  This is (apparently)
compiled from a VHDL source file called alt_vtl.vhd, which
is supplied by Altera; for reference, the top section of
this file contains the following (paraphrased):
---------------------------------------------
-- Copyright (c) 1995 by Altera Corporation.
-- FILENAME     :    alt_vtl.vhd (3.0)
-- DATE CREATED :    Mon Jul 24 15:54:24 1995
-- LIBRARY      :    alt_vtl
-- REVISION     :    1.0
-- LOGIC SYSTEM :    IEEE-1164
---------------------------------------------

There are at least two versions of this file that I know
of: version 3.0 as shown above, and version 2.2.  I'm not
precisely sure which version we are using (I'm don't know
who originally set up our design environment), but I suspect
that the behavior I'm describing applies to both versions.

Also included in Altera's distribution is a source file
alt_vtl.cmp, the top section of this file contains the
following:
--------------------------------------------------
-- Copyright (c) 1995 by Altera Corporation.
-- FILENAME     :    alt_vtl.cmp
-- FILE CONTENTS:    VITAL Component Package (3.0)
-- DATE CREATED :    Fri Feb 17 15:54:24 1995
-- LIBRARY      :    alt_vtl
-- REVISION     :    1.0
-- LOGIC SYSTEM :    IEEE-1164
--------------------------------------------------

When compiled, this file generates a package called VCOMPONENTS.
The cell primatives contained in this package are what
are referenced in .vho files.  Both alt_vtl.vhd and alt_vtl.cmp
contain the following reference:
library IEEE;
use IEEE.VITAL_Timing.all;

I perused around our system until I found what apparently is the
source file for the IEEE VITAL_Timing package.  Inspecting the
source, one finds the following 3 procedures:

PROCEDURE VitalPathDelay
PROCEDURE VitalPathDelay01
PROCEDURE VitalPathDelay01Z

Each of these procedures reference a procedure called
VitalGlitch, which in turn references a procedure called
ReportGlitch.  It is ReportGlitch, I believe, which is generating
glitch messages pertaining to Altera's .vho files in the
simulation monitor window.  An example similar to these messages
is the following:

#    Time: 34338500 ps  Iteration: 1  Instance:/\/ .../... \/inv_2085
# ** Warning: VitalGlitch: GLITCH Detected on port Y ;


************** The question: **************
My question, at long last, is this:  Is there a way to suppress
the generation of these glitch messages?  Note that Mentor provides
a switch ("-noglitch") that can be included upon invocation of
the QHPro simulation, however, using this does not result in
glitch message suppression.  What would probably be appropriate
would be to turn off glitch detection altogether.  I suspect that
this would save some CPU overhead during simulation runs.

One way I can think of would be to turn off the timing checks
on some of the cell primatives in the .vho file by using a
GENERIC map reference.  Seems like this would be a major pain
because one would either have to manually add the generic references
to the appropriate cells or have a script go in and auto detect
and append generics to the cells of interest.

I contacted Mentor about this and they said they know of no
problem with the -noglitch switch and suggested contacting
the CPLD/FPGA kit vendor.  I then approached Altera (a while
ago) and they have not yet given me an answer on this issue.

Thank you for any information pertaining to this topic.

--------------------------
Lawrence Peregrim
MIT Lincoln Lab

--------------------------



Tue, 23 May 2000 03:00:00 GMT  
 (Altera) VITAL libraries

To suppress Altera glitch (and other) messages, have a look inside the
VITAL implementation of the Altera components. Among other defaults, you'll
find

   CONSTANT DefGlitchMsgOn      : BOOLEAN       := FALSE;

If your file has TRUE, the solution is obvious. If not, just trace back
where the default value is overridden and fix that spot.

Hope this helps,
--
Hendrik De Vloed -- A4000/40 -- check out Aminet:hard/hack/lcdaemon.lha
(these are my private opinions which may oppose those of my employer, my
family or other basic laws of nature)
<To reply, replace the company name by plain "barco">



Quote:
> My question, at long last, is this:  Is there a way to suppress
> the generation of these glitch messages?  Note that Mentor provides
> a switch ("-noglitch") that can be included upon invocation of
> the QHPro simulation, however, using this does not result in
> glitch message suppression.  What would probably be appropriate
> would be to turn off glitch detection altogether.  I suspect that
> this would save some CPU overhead during simulation runs.



Fri, 26 May 2000 03:00:00 GMT  
 
 [ 2 post ] 

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